Re: [PATCH v3 2/4] clk: fsl-sai: Add i.MX8M support with 8 byte register offset

[Brian Masney]

On Sat, Apr 04, 2026 at 08:33:26PM +0200, Marek Vasut wrote:
> The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
> shifted by +8 bytes and requires additional bus clock. Add support for
> the i.MX8M variant of the IP with this register shift and additional
> clock.
> 
> Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
> Signed-off-by: Marek Vasut <marex@xxxxxxxxxxxx>

Reviewed-by: Brian Masney <bmasney@xxxxxxxxxx>