RE: [PATCH v3 11/15] dmaengine: sh: rz-dmac: Add cyclic DMA support

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@xxxxxxxxx>
> Sent: 07 April 2026 14:35
> Subject: [PATCH v3 11/15] dmaengine: sh: rz-dmac: Add cyclic DMA support
> 
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> 
> Add cyclic DMA support to the RZ DMAC driver. A per-channel status bit is introduced to mark cyclic
> channels and is set during the DMA prepare callback. The IRQ handler checks this status bit and calls
> vchan_cyclic_callback() accordingly.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> ---
> 
> Changes in v3:
> - updated rz_dmac_lmdesc_recycle() to restore the lmdesc->nxla
> - in rz_dmac_prepare_descs_for_cyclic() update directly the
>   desc->start_lmdesc with the descriptor pointer insted of the
>   descriptor address
> - used rz_dmac_lmdesc_addr() to compute the descritor address
> - set channel->status = 0 in rz_dmac_free_chan_resources()
> - in rz_dmac_prep_dma_cyclic() check for invalid periods or buffer len
>   and limit the critical area protected by spinlock
> - set channel->status = 0 in rz_dmac_terminate_all()
> - updated rz_dmac_calculate_residue_bytes_in_vd() to use
>   rz_dmac_lmdesc_addr()
> - dropped goto in rz_dmac_irq_handler_thread() as it is not needed
>   anymore; dropped also the local variable desc
> 
> Changes in v2:
> - none
> 
>  drivers/dma/sh/rz-dmac.c | 144 +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 138 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 8fbccabc94e4..f7133ac6af60
> 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -35,6 +35,7 @@
>  enum  rz_dmac_prep_type {
>  	RZ_DMAC_DESC_MEMCPY,
>  	RZ_DMAC_DESC_SLAVE_SG,
> +	RZ_DMAC_DESC_CYCLIC,
>  };
> 
>  struct rz_lmdesc {
> @@ -67,9 +68,11 @@ struct rz_dmac_desc {
>  /**
>   * enum rz_dmac_chan_status: RZ DMAC channel status
>   * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callbacks
> + * @RZ_DMAC_CHAN_STATUS_CYCLIC: Channel is cyclic
>   */
>  enum rz_dmac_chan_status {
>  	RZ_DMAC_CHAN_STATUS_PAUSED,
> +	RZ_DMAC_CHAN_STATUS_CYCLIC,
>  };
> 
>  struct rz_dmac_chan {
> @@ -191,6 +194,7 @@ struct rz_dmac {
> 
>  /* LINK MODE DESCRIPTOR */
>  #define HEADER_LV			BIT(0)
> +#define HEADER_WBD			BIT(2)
> 
>  #define RZ_DMAC_MAX_CHAN_DESCRIPTORS	16
>  #define RZ_DMAC_MAX_CHANNELS		16
> @@ -272,9 +276,12 @@ static void rz_lmdesc_setup(struct rz_dmac_chan *channel,  static void
> rz_dmac_lmdesc_recycle(struct rz_dmac_chan *channel)  {
>  	struct rz_lmdesc *lmdesc = channel->lmdesc.head;
> +	u32 nxla = channel->lmdesc.base_dma;
> 
>  	while (!(lmdesc->header & HEADER_LV)) {
>  		lmdesc->header = 0;
> +		nxla += sizeof(*lmdesc);
> +		lmdesc->nxla = nxla;
>  		lmdesc++;
>  		if (lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
>  			lmdesc = channel->lmdesc.base;
> @@ -429,6 +436,57 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
>  	rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid);  }
> 
> +static void rz_dmac_prepare_descs_for_cyclic(struct rz_dmac_chan
> +*channel) {
> +	struct dma_chan *chan = &channel->vc.chan;
> +	struct rz_dmac *dmac = to_rz_dmac(chan->device);
> +	struct rz_dmac_desc *d = channel->desc;
> +	size_t period_len = d->sgcount;
> +	struct rz_lmdesc *lmdesc;
> +	size_t buf_len = d->len;
> +	size_t periods = buf_len / period_len;
> +
> +	lockdep_assert_held(&channel->vc.lock);
> +
> +	channel->chcfg |= CHCFG_SEL(channel->index) | CHCFG_DMS;
> +
> +	if (d->direction == DMA_DEV_TO_MEM) {
> +		channel->chcfg |= CHCFG_SAD;
> +		channel->chcfg &= ~CHCFG_REQD;
> +	} else {
> +		channel->chcfg |= CHCFG_DAD | CHCFG_REQD;
> +	}
> +
> +	lmdesc = channel->lmdesc.tail;
> +	d->start_lmdesc = lmdesc;
> +
> +	for (size_t i = 0; i < periods; i++) {
> +		if (d->direction == DMA_DEV_TO_MEM) {
> +			lmdesc->sa = d->src;
> +			lmdesc->da = d->dest + (i * period_len);
> +		} else {
> +			lmdesc->sa = d->src + (i * period_len);
> +			lmdesc->da = d->dest;
> +		}
> +
> +		lmdesc->tb = period_len;
> +		lmdesc->chitvl = 0;
> +		lmdesc->chext = 0;
> +		lmdesc->chcfg = channel->chcfg;
> +		lmdesc->header = HEADER_LV | HEADER_WBD;
> +
> +		if (i == periods - 1)
> +			lmdesc->nxla = rz_dmac_lmdesc_addr(channel, d->start_lmdesc);
> +
> +		if (++lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
> +			lmdesc = channel->lmdesc.base;
> +	}
> +
> +	channel->lmdesc.tail = lmdesc;
> +
> +	rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); }
> +
>  static void rz_dmac_xfer_desc(struct rz_dmac_chan *chan)  {
>  	struct virt_dma_desc *vd;
> @@ -450,6 +508,10 @@ static void rz_dmac_xfer_desc(struct rz_dmac_chan *chan)
>  	case RZ_DMAC_DESC_SLAVE_SG:
>  		rz_dmac_prepare_descs_for_slave_sg(chan);
>  		break;
> +
> +	case RZ_DMAC_DESC_CYCLIC:
> +		rz_dmac_prepare_descs_for_cyclic(chan);
> +		break;
>  	}
> 
>  	rz_dmac_enable_hw(chan);
> @@ -500,6 +562,8 @@ static void rz_dmac_free_chan_resources(struct dma_chan *chan)
>  		channel->mid_rid = -EINVAL;
>  	}
> 
> +	channel->status = 0;
> +
>  	spin_unlock_irqrestore(&channel->vc.lock, flags);

Maybe create a patch to convert all the spin_{lock,unlock} with guard()
in this driver.

Cheers,
Biju