Re: [PATCH 1/3] staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@xxxxxxxxx>
>
> Fix various spacing issues reported by checkpatch.pl to improve code
> readability and conform to the Linux kernel coding style.
>
> Specifically, this patch:
> - Adds missing spaces around binary operators (| , >> , << , + , &).
> - Corrects the spacing in bitwise expressions within function calls.
> - Ensures consistent use of whitespace in arithmetic operations.
>
I think this section above is unnecessary as you have already mentioned 
that this patch handles spacing.
> These changes are purely cosmetic and do not alter the functional
> behavior of the driver.
>
> Signed-off-by: tas0dev <osjin83@xxxxxxxxx>
Your Signed-off-by tag must use you real name(First Last) to comply 
with the Developers Certificate of Origin. You should also use your
real name for sending emails.
> ---
>  .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   | 44 +++++++++----------
>  1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> index 7fac1c2ba8e0..cfa00775341b 100644
> --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> @@ -19,7 +19,7 @@ static	u32 phy_CalculateBitShift(u32 BitMask)
>  	u32 i;
>  
>  	for (i = 0; i <= 31; i++) {
> -		if (((BitMask>>i) &  0x1) == 1)
> +		if (((BitMask >> i) &  0x1) == 1)
>  			break;
>  	}
>  	return i;
> @@ -109,18 +109,18 @@ static u32 phy_RFSerialRead_8723B(
>  	NewOffset = Offset;
>  
>  	if (eRFPath == RF_PATH_A) {
> -		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
> -		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
> +		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
> +		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
>  	} else {
> -		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
> -		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
> +		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
> +		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
>  	}
>  
> -	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
> -	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
> +	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
> +	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
>  
>  	udelay(10);
>  
> @@ -129,16 +129,16 @@ static u32 phy_RFSerialRead_8723B(
>  	udelay(10);
>  
>  	if (eRFPath == RF_PATH_A)
> -		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
> +		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
>  	else if (eRFPath == RF_PATH_B)
> -		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
> +		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
>  
>  	if (RfPiEnable) {
>  		/*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
> -		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
> +		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
>  	} else {
>  		/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
> -		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
> +		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
>  	}
>  	return retValue;
>  
> @@ -203,7 +203,7 @@ static void phy_RFSerialWrite_8723B(
>  	/*  */
>  	/*  Put write addr in [5:0]  and write data in [31:16] */
>  	/*  */
> -	DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;	/*  T65 RF */
> +	DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;	/*  T65 RF */
>  	/*  */
>  	/*  Write Operation */
>  	/*  */
> @@ -266,7 +266,7 @@ void PHY_SetRFReg_8723B(
>  	if (BitMask != bRFRegOffsetMask) {
>  		Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
>  		BitShift =  phy_CalculateBitShift(BitMask);
> -		Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
> +		Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
>  	}
>  
>  	phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
> @@ -385,11 +385,11 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
>  
>  	/*  Enable BB and RF */
>  	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
> -	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
> +	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1));
>  
>  	rtw_write32(Adapter, 0x948, 0x280);	/*  Others use Antenna S1 */
>  
> -	rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
> +	rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
>  
>  	msleep(1);
>  
> @@ -397,7 +397,7 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
>  
>  	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
>  
> -	rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
> +	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
>  
>  	/*  */
>  	/*  Config BB and AGC */
> @@ -631,7 +631,7 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
>  
>  		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
>  
> -		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
> +		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
>  		break;
>  
>  	/* 40 MHz channel*/
> @@ -641,11 +641,11 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
>  		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
>  
>  		/*  Set Control channel to upper or lower. These settings are required only for 40MHz */
> -		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
> +		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
>  
>  		PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
>  
> -		PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
> +		PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
>  		break;
>  	default:
>  		break;