[PATCH 1/16] riscv: Introduce instruction table generation

[Charlie Jenkins]

Eliminate the need to hand-write riscv instructions by using a shell
script to autogenerate a header from an instruction table. This is modeled
after the syscall table infrastructure.

The table is generated externally by riscv-unified-db [1], but is
in a simple format to make it possible to use other tools or modify
manually.

[1] https://github.com/riscv-software-src/riscv-unified-db

Signed-off-by: Charlie Jenkins <thecharlesjenkins@xxxxxxxxx>

---

This change immediately modifies all of the riscv_insn_* macros. I don't
have a clean way of sharing my test cases but what I did was compare the
old and new versions of the functions using the following test case:

    for (unsigned int i = 0; i < ((1ULL << 32) - 1); i++) {\
        bool old = riscv_insn_is_##name(i);\
        bool new = new_riscv_insn_is_##name(i);\
        if (old != new) {\
            printf(#name " %u\n", i);\
        }\
    }

    for (unsigned int i = 0; i < ((1ULL << 32) - 1); i++) {\
        bool old = riscv_insn_is_##name(i);\
        bool new = new_riscv_insn_is_##name(i);\
\
        if (old != new) {\
            printf(#name " %u\n", i);\
            return;\
        }\
    }

void check()
{
    check_64(auipc)
    check_64(jalr)
    check_64(jal)
    check_64(beq)
    check_64(bne)
    check_64(blt)
    check_64(bge)
    check_64(bltu)
    check_64(bgeu)
    check_64(ebreak)
    check_64(sret)
    check_64(fence)

    check_32(c_jr)
    check_32(c_jalr)
    check_32(c_j)
    check_32(c_beqz)
    check_32(c_bnez)
    check_32(c_ebreak)
}

This does a simple brute force to check all possible numbers. The
only difference with the new version is that the fence instruction
refers to the literal "fence" instruction whereas the previous version
could have matched on to fence, fence.i, or fence.tso. This does not
make a material difference because riscv_insn_is_fence() isn't currently
in use.
---
 arch/riscv/Makefile           |    3 +
 arch/riscv/include/asm/Kbuild |    1 +
 arch/riscv/include/asm/insn.h |   72 +-
 arch/riscv/tools/Makefile     |   22 +
 arch/riscv/tools/insn.tbl     | 1391 +++++++++++++++++++++++++++++++++
 arch/riscv/tools/insn_tbl.sh  |  263 +++++++
 6 files changed, 1710 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/tools/Makefile
 create mode 100644 arch/riscv/tools/insn.tbl
 create mode 100755 arch/riscv/tools/insn_tbl.sh

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4c6de57f65ef..d665b015988b 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -171,6 +171,9 @@ BOOT_TARGETS := Image Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zs
 
 all:	$(notdir $(KBUILD_IMAGE))
 
+archprepare:
+	$(Q)$(MAKE) $(build)=arch/riscv/tools insn
+
 loader.bin: loader
 Image.gz Image.bz2 Image.lz4 Image.lzma Image.lzo Image.zst Image.xz loader xipImage vmlinuz.efi: Image
 
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index bd5fc9403295..82feba7b0eb5 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -2,6 +2,7 @@
 syscall-y += syscall_table_32.h
 syscall-y += syscall_table_64.h
 
+generated-y += insn_gen.h
 generic-y += early_ioremap.h
 generic-y += flat.h
 generic-y += fprobe.h
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index c3005573e8c9..d562b2b40ba1 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -8,6 +8,36 @@
 
 #include <linux/bits.h>
 
+/*
+ * Generate a function to check if a sequence of bits matches an instruction
+ */
+#define __RISCV_INSN_FUNCS(name)							\
+static __always_inline bool riscv_insn_is_##name(u32 _insn)				\
+{											\
+	BUILD_BUG_ON(~(riscv_insn_##name##_MASK) & (riscv_insn_##name##_MATCH));	\
+	return (_insn & (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH);	\
+}
+
+/*
+ * Generate a function to check if a sequence of bits matches an instruction
+ * with constraints. Some instructions require inputs to be specific values.
+ */
+#define __RISCV_INSN_FUNCS_CONSTRAINED(name, constraints)				\
+static __always_inline bool riscv_insn_is_##name(u32 _insn)				\
+{											\
+	BUILD_BUG_ON(~(riscv_insn_##name##_MASK) & (riscv_insn_##name##_MATCH));	\
+	return ((_insn & (riscv_insn_##name##_MASK)) == (riscv_insn_##name##_MATCH)) && \
+	       (constraints);								\
+}
+
+#define __RISCV_INSN_FUNCS_UNSUPPORTED(name)				\
+static __always_inline bool riscv_insn_is_##name(u32 _insn)		\
+{									\
+	return 0;							\
+}
+
+#include <asm/insn_gen.h>
+
 #define RV_INSN_FUNCT3_MASK	GENMASK(14, 12)
 #define RV_INSN_FUNCT3_OPOFF	12
 #define RV_INSN_OPCODE_MASK	GENMASK(6, 0)
@@ -233,36 +263,6 @@
 #define __INSN_OPCODE_MASK	_UL(0x7F)
 #define __INSN_BRANCH_OPCODE	_UL(RVG_OPCODE_BRANCH)
 
-#define __RISCV_INSN_FUNCS(name, mask, val)				\
-static __always_inline bool riscv_insn_is_##name(u32 code)		\
-{									\
-	BUILD_BUG_ON(~(mask) & (val));					\
-	return (code & (mask)) == (val);				\
-}									\
-
-#if __riscv_xlen == 32
-/* C.JAL is an RV32C-only instruction */
-__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
-#else
-#define riscv_insn_is_c_jal(opcode) 0
-#endif
-__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
-__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
-__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
-__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
-__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
-__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
-__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
-__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
-__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
-__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
-__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)
-__RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)
-__RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)
-__RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)
-__RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)
-__RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);
-
 /* special case to catch _any_ system instruction */
 static __always_inline bool riscv_insn_is_system(u32 code)
 {
@@ -275,18 +275,6 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
 	return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
 }
 
-static __always_inline bool riscv_insn_is_c_jr(u32 code)
-{
-	return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
-	       (code & RVC_INSN_J_RS1_MASK) != 0;
-}
-
-static __always_inline bool riscv_insn_is_c_jalr(u32 code)
-{
-	return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
-	       (code & RVC_INSN_J_RS1_MASK) != 0;
-}
-
 #define INSN_MATCH_LB		0x3
 #define INSN_MASK_LB		0x707f
 #define INSN_MATCH_LH		0x1003
diff --git a/arch/riscv/tools/Makefile b/arch/riscv/tools/Makefile
new file mode 100644
index 000000000000..5f40439c12e9
--- /dev/null
+++ b/arch/riscv/tools/Makefile
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+
+gen := arch/$(ARCH)/include/generated/asm
+insn_tbl := $(src)/insn_tbl.sh
+insn := $(src)/insn.tbl
+
+gen-y := $(gen)/insn_gen.h
+
+targets += $(addprefix ../../../,$(gen-y))
+
+PHONY += insn
+
+insn:	$(gen-y)
+
+# Create output directory if not already present
+$(shell mkdir -p $(gen))
+
+quiet_cmd_insn_tbl = INST_TBL  $@
+      cmd_insn_tbl = $(CONFIG_SHELL) $(insn_tbl) $< $@
+
+$(gen)/insn_gen.h: $(insn) $(insn_tbl) FORCE
+	$(call if_changed,insn_tbl)
diff --git a/arch/riscv/tools/insn.tbl b/arch/riscv/tools/insn.tbl
new file mode 100644
index 000000000000..56797903b141
--- /dev/null
+++ b/arch/riscv/tools/insn.tbl
@@ -0,0 +1,1391 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# GENERATED WITH https://github.com/riscv-software-src/riscv-unified-db
+# "bundle exec rake gen:insn_table"
+#
+# Each line of the instruction table should have the following format:
+# NAME BASE FIXED_BITS [VARIABLE_LIST]
+# NAME                        instruction name
+# BASE                        instruction base size (common[,(32|64)])
+# FIXED_BITS                  bitfields of the fixed bits of an instruction concatenated with |
+#                             each continuous grouping of fixed bits is in the format of bits<offset
+# all instruction variables in the form of <var>[-<sign_extend>-][<<left_shift><][!<constraint>...]
+#                             if the variable requires sign extension, surround the index to sign extend at in '-'
+#                             if the variable requires left shifting, surround the left shift amount in '<'
+#                             a "constraint" is an integer value that is invalid for this variable
+# VARIABLE_LIST               a variable sized list of all variables in the instruction definition
+#                             in the form of name[~][<num][!num...]=(high[-low])|...
+#                             symbols after the name represent different modifiers:
+#                                 ~ sign extension, can only appear once
+#                                 < left shift by 'num' amount on extraction, can only appear once
+#                                 ! mark 'num' as an invalid input for this variable, any number may appear
+andn common 0100000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+clmul common 0000101<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+clmulh common 0000101<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+orn common 0100000<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rev8 common,32 011010011000<20|101<12|0010011<0 xs1=19-15 xd=11-7
+rev8 common,64 011010111000<20|101<12|0010011<0 xs1=19-15 xd=11-7
+rol common 0110000<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rolw 64 0110000<25|001<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+ror common 0110000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+rori common,32 0110000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+rori common,64 011000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+roriw 64 0110000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+rorw 64 0110000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+xnor common 0100000<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+c.add common 1001<12|10<0 xs2!0=6-2 xd!0=11-7
+c.addi common 000<13|01<0 imm!0=12|6-2 xd!0=11-7
+c.addi16sp common 011<13|00010<7|01<0 imm!0<4=12|4-3|5|2|6
+c.addi4spn common 000<13|00<0 imm!0<2=10-7|12-11|5|6 xd=4-2
+c.addiw 64 001<13|01<0 imm=12|6-2 xd!0=11-7
+c.addw 64 100111<10|01<5|01<0 xs2=4-2 xd=9-7
+c.and common 100011<10|11<5|01<0 xs2=4-2 xd=9-7
+c.andi common 100<13|10<10|01<0 imm=12|6-2 xd=9-7
+c.beqz common 110<13|01<0 imm~<1=12|6-5|2|11-10|4-3 xs1=9-7
+c.bnez common 111<13|01<0 imm~<1=12|6-5|2|11-10|4-3 xs1=9-7
+c.ebreak common 1001000000000010<0
+c.j common 101<13|01<0 imm~<1=12|8|10-9|6|7|2|11|5-3
+c.jal 32 001<13|01<0 imm~<1=12|8|10-9|6|7|2|11|5-3
+c.jalr common 1001<12|0000010<0 xs1!0=11-7
+c.jr common 1000<12|0000010<0 xs1!0=11-7
+c.ld common,32 011<13|00<0 imm<3=6-5|12-10 xd!1!3!5!7=4-2 xs1=9-7
+c.ld common,64 011<13|00<0 imm<3=6-5|12-10 xd=4-2 xs1=9-7
+c.ldsp common,32 011<13|10<0 imm<3=4-2|12|6-5 xd!0!1!3!5!7=11-7
+c.ldsp common,64 011<13|10<0 imm<3=4-2|12|6-5 xd=11-7
+c.li common 010<13|01<0 imm=12|6-2 xd!0=11-7
+c.lui common 011<13|01<0 imm<12=12|6-2 xd!0!2=11-7
+c.lw common 010<13|00<0 imm<2=5|12-10|6 xd=4-2 xs1=9-7
+c.lwsp common 010<13|10<0 imm<2=3-2|12|6-4 xd!0=11-7
+c.mv common 1000<12|10<0 xd!0=11-7 xs2!0=6-2
+c.nop common 0000000000000001<0
+c.or common 100011<10|10<5|01<0 xs2=4-2 xd=9-7
+c.sd common,32 111<13|00<0 imm<3=6-5|12-10 xs2!1!3!5!7=4-2 xs1=9-7
+c.sd common,64 111<13|00<0 imm<3=6-5|12-10 xs2=4-2 xs1=9-7
+c.sdsp common,32 111<13|10<0 xs2!1!3!5!7=6-2 imm<3=9-7|12-10
+c.sdsp common,64 111<13|10<0 xs2=6-2 imm<3=9-7|12-10
+c.slli common,32 0000<12|10<0 shamt!0=6-2 xd=11-7
+c.slli common,64 000<13|10<0 shamt!0=12|6-2 xd=11-7
+c.srai common,32 100001<10|01<0 shamt!0=6-2 xd=9-7
+c.srai common,64 100<13|01<10|01<0 shamt!0=12|6-2 xd=9-7
+c.srli common,32 100000<10|01<0 shamt!0=6-2 xd=9-7
+c.srli common,64 100<13|00<10|01<0 shamt!0=12|6-2 xd=9-7
+c.sub common 100011<10|00<5|01<0 xs2=4-2 xd=9-7
+c.subw 64 100111<10|00<5|01<0 xs2=4-2 xd=9-7
+c.sw common 110<13|00<0 imm<2=5|12-10|6 xs2=4-2 xs1=9-7
+c.swsp common 110<13|10<0 imm<2=8-7|12-9 xs2=6-2
+c.xor common 100011<10|01<5|01<0 xs2=4-2 xd=9-7
+fadd.d common 0000001<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.d common 111000100000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.d.l 64 110100100010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.lu 64 110100100011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.s common 010000100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.d.w common 110100100000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.d.wu common 110100100001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.l.d 64 110000100010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.d 64 110000100011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.s.d common 010000000001<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.w.d common 110000100000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.d common 110000100001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvtmod.w.d common 110000101000<20|1010011<0 fs1=19-15 rm!0!2!3!4!5!6!7=14-12 xd=11-7
+fdiv.d common 0001101<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.d common 1010001<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fld common 011<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+fle.d common 1010001<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.d common 1010001<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fli.d common 111100100001<20|000<12|1010011<0 xs1=19-15 fd=11-7
+flt.d common 1010001<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.d common 1010001<25|101<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fmadd.d common 01<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.d common 0010101<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmaxm.d common 0010101<25|011<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.d common 0010101<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fminm.d common 0010101<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.d common 01<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.d common 0001001<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmv.d.x 64 111100100000<20|000<12|1010011<0 xs1=19-15 fd=11-7
+fmv.x.d 64 111000100000<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvh.x.d 32 111000100001<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvp.d.x 32 1011001<25|000<12|1010011<0 xs2=24-20 xs1=19-15 fd=11-7
+fnmadd.d common 01<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.d common 01<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fround.d common 010000100100<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+froundnx.d common 010000100101<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsd common 011<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+fsgnj.d common 0010001<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.d common 0010001<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.d common 0010001<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsqrt.d common 010110100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.d common 0000101<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fadd.s common 0000000<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.s common 111000000000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.l.s 64 110000000010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.s 64 110000000011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.s.l 64 110100000010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.lu 64 110100000011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.w common 110100000000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.wu common 110100000001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.w.s common 110000000000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.s common 110000000001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fdiv.s common 0001100<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.s common 1010000<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fle.s common 1010000<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.s common 1010000<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+flt.s common 1010000<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.s common 1010000<25|101<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+flw common 010<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+fmadd.s common 00<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.s common 0010100<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.s common 0010100<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.s common 00<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.s common 0001000<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmv.w.x common 111100000000<20|000<12|1010011<0 xs1=19-15 fd=11-7
+fmv.x.w common 111000000000<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fnmadd.s common 00<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.s common 00<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fsgnj.s common 0010000<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.s common 0010000<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.s common 0010000<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsqrt.s common 010110000000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.s common 0000100<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fsw common 010<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+hfence.gvma common 0110001<25|000000001110011<0 xs2=24-20 xs1=19-15
+hfence.vvma common 0010001<25|000000001110011<0 xs2=24-20 xs1=19-15
+hlv.b common 011000000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.bu common 011000000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.d 64 011011000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.h common 011001000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.hu common 011001000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.w common 011010000000<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlv.wu 64 011010000001<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlvx.hu common 011001000011<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hlvx.wu common 011010000011<20|100<12|1110011<0 xs1=19-15 xd=11-7
+hsv.b common 0110001<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.d 64 0110111<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.h common 0110011<25|100000001110011<0 xs2=24-20 xs1=19-15
+hsv.w common 0110101<25|100000001110011<0 xs2=24-20 xs1=19-15
+add common 0000000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+addi common 000<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+addiw 64 000<12|0011011<0 imm=31-20 xs1=19-15 xd=11-7
+addw 64 0000000<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+and common 0000000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+andi common 111<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+auipc common 0010111<0 imm<12=31-12 xd=11-7
+beq common 000<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bge common 101<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bgeu common 111<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+blt common 100<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bltu common 110<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+bne common 001<12|1100011<0 imm~<1=31|7|30-25|11-8 xs2=24-20 xs1=19-15
+ebreak common 00000000000100000000000001110011<0
+ecall common 00000000000000000000000001110011<0
+fence.tso common 100000110011<20|000<12|0001111<0 xs1=19-15 xd=11-7
+fence common 000<12|0001111<0 fm=31-28 pred=27-24 succ=23-20 xs1=19-15 xd=11-7
+jal common 1101111<0 imm~<1=31|19-12|20|30-21 xd=11-7
+jalr common 000<12|1100111<0 imm~=31-20 xs1=19-15 xd=11-7
+lb common 000<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+lbu common 100<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+ld common,32 011<12|0000011<0 imm=31-20 xs1=19-15 xd!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=11-7
+ld common,64 011<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+lh common 001<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+lhu common 101<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+lui common 0110111<0 imm<12=31-12 xd=11-7
+lw common 010<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+lwu 64 110<12|0000011<0 imm=31-20 xs1=19-15 xd=11-7
+mret common 00110000001000000000000001110011<0
+or common 0000000<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+ori common 110<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+sb common 000<12|0100011<0 imm=31-25|11-7 xs2=24-20 xs1=19-15
+sd common,32 011<12|0100011<0 imm=31-25|11-7 xs2!1!3!5!7!9!11!13!15!17!19!21!23!25!27!29!31=24-20 xs1=19-15
+sd common,64 011<12|0100011<0 imm~=31-25|11-7 xs2=24-20 xs1=19-15
+sh common 001<12|0100011<0 imm=31-25|11-7 xs2=24-20 xs1=19-15
+sll common 0000000<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+slli common,32 0000000<25|001<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+slli common,64 000000<26|001<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+slliw 64 0000000<25|001<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+sllw 64 0000000<25|001<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+slt common 0000000<25|010<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+slti common 010<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+sltiu common 011<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+sltu common 0000000<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sra common 0100000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+srai common,32 0100000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+srai common,64 010000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+sraiw 64 0100000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+sraw 64 0100000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+srl common 0000000<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+srli common,32 0000000<25|101<12|0010011<0 shamt=24-20 xs1=19-15 xd=11-7
+srli common,64 000000<26|101<12|0010011<0 shamt=25-20 xs1=19-15 xd=11-7
+srliw 64 0000000<25|101<12|0011011<0 shamt=24-20 xs1=19-15 xd=11-7
+srlw 64 0000000<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+sub common 0100000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+subw 64 0100000<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+sw common 010<12|0100011<0 imm=31-25|11-7 xs2=24-20 xs1=19-15
+wfi common 00010000010100000000000001110011<0
+xor common 0000000<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+xori common 100<12|0010011<0 imm=31-20 xs1=19-15 xd=11-7
+div common 0000001<25|100<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+divu common 0000001<25|101<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+divuw 64 0000001<25|101<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+divw 64 0000001<25|100<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+mul common 0000001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulh common 0000001<25|001<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulhsu common 0000001<25|010<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulhu common 0000001<25|011<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mulw 64 0000001<25|000<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+rem common 0000001<25|110<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+remu common 0000001<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+remuw 64 0000001<25|111<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+remw 64 0000001<25|110<12|0111011<0 xs2=24-20 xs1=19-15 xd=11-7
+fadd.q common 0000011<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fclass.q common 111001100000<20|001<12|1010011<0 fs1=19-15 xd=11-7
+fcvt.d.q common 010000100011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.h.q common 010001000011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.l.q 64 110001100010<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.lu.q 64 110001100011<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.q.d common 010001100001<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.h common 010001100010<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.l 64 110101100010<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.lu 64 110101100011<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.s common 010001100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.q.w common 110101100000<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.q.wu common 110101100001<20|1010011<0 xs1=19-15 rm=14-12 fd=11-7
+fcvt.s.q common 010000000011<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fcvt.w.q common 110001100000<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fcvt.wu.q common 110001100001<20|1010011<0 fs1=19-15 rm=14-12 xd=11-7
+fdiv.q common 0001111<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+feq.q common 1010011<25|010<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fle.q common 1010011<25|000<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fleq.q common 1010011<25|100<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fli.q common 111101100001<20|000<12|1010011<0 xs1=19-15 fd=11-7
+flq common 100<12|0000111<0 imm=31-20 xs1=19-15 fd=11-7
+flt.q common 1010011<25|001<12|1010011<0 fs2=24-20 fs1=19-15 xd=11-7
+fltq.q common 1010011<25|101<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmadd.q common 11<25|1000011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmax.q common 0010111<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmaxm.q common 0010111<25|011<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmin.q common 0010111<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fminm.q common 0010111<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fmsub.q common 11<25|1000111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmul.q common 0001011<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fmvh.x.q 64 111001100001<20|000<12|1010011<0 fs1=19-15 xd=11-7
+fmvp.q.x 64 1011011<25|000<12|1010011<0 xs2=24-20 xs1=19-15 fd=11-7
+fnmadd.q common 11<25|1001111<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fnmsub.q common 11<25|1001011<0 fs3=31-27 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+fround.q common 010001100100<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+froundnx.q common 010001100101<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsgnj.q common 0010011<25|000<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjn.q common 0010011<25|001<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsgnjx.q common 0010011<25|010<12|1010011<0 fs2=24-20 fs1=19-15 fd=11-7
+fsq common 100<12|0100111<0 imm=31-25|11-7 fs2=24-20 xs1=19-15
+fsqrt.q common 010111100000<20|1010011<0 fs1=19-15 rm=14-12 fd=11-7
+fsub.q common 0000111<25|1010011<0 fs2=24-20 fs1=19-15 rm=14-12 fd=11-7
+sfence.vma common 0001001<25|000000001110011<0 xs2=24-20 xs1=19-15
+sret common 00010000001000000000000001110011<0
+dret common 01111011001000000000000001110011<0
+sctrclr common 00010000010000000000000001110011<0
+mnret common 01110000001000000000000001110011<0
+hinval.gvma common 0110011<25|000000001110011<0 xs2=24-20 xs1=19-15
+hinval.vvma common 0010011<25|000000001110011<0 xs2=24-20 xs1=19-15
+sfence.inval.ir common 00011000000100000000000001110011<0
+sfence.w.inval common 00011000000000000000000001110011<0
+sinval.vma common 0001011<25|000000001110011<0 xs2=24-20 xs1=19-15
+vaadd.vv common 001001<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vaadd.vx common 001001<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vaaddu.vv common 001000<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vaaddu.vx common 001000<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vadc.vim common 0100000<25|011<12|1010111<0 vs2=24-20 imm=19-15 vd=11-7
+vadc.vvm common 0100000<25|000<12|1010111<0 vs2=24-20 vs1=19-15 vd=11-7
+vadc.vxm common 0100000<25|100<12|1010111<0 vs2=24-20 xs1=19-15 vd=11-7
+vadd.vi common 000000<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm=19-15 vd=11-7
+vadd.vv common 000000<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vadd.vx common 000000<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vand.vi common 001001<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm=19-15 vd=11-7
+vand.vv common 001001<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vand.vx common 001001<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vasub.vv common 001011<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vasub.vx common 001011<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vasubu.vv common 001010<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vasubu.vx common 001010<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vcompress.vm common 0101111<25|010<12|1010111<0 vs2=24-20 vs1=19-15 vd=11-7
+vcpop.m common 010000<26|10000010<12|1010111<0 vm=25-25 vs2=24-20 xd=11-7
+vdiv.vv common 100001<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vdiv.vx common 100001<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vdivu.vv common 100000<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vdivu.vx common 100000<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vfadd.vf common 000000<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfadd.vv common 000000<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfclass.v common 010011<26|10000001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.f.x.v common 010010<26|00011001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.f.xu.v common 010010<26|00010001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.rtz.x.f.v common 010010<26|00111001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.rtz.xu.f.v common 010010<26|00110001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.x.f.v common 010010<26|00001001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfcvt.xu.f.v common 010010<26|00000001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfdiv.vf common 100000<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfdiv.vv common 100000<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfirst.m common 010000<26|10001010<12|1010111<0 vm=25-25 vs2=24-20 xd=11-7
+vfmacc.vf common 101100<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmacc.vv common 101100<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmadd.vf common 101000<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmadd.vv common 101000<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmax.vf common 000110<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmax.vv common 000110<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmerge.vfm common 0101110<25|101<12|1010111<0 vs2=24-20 fs1=19-15 vd=11-7
+vfmin.vf common 000100<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmin.vv common 000100<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmsac.vf common 101110<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmsac.vv common 101110<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmsub.vf common 101010<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmsub.vv common 101010<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmul.vf common 100100<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfmul.vv common 100100<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vfmv.f.s common 0100001<25|00000001<12|1010111<0 vs2=24-20 fd=11-7
+vfmv.s.f common 010000100000<20|101<12|1010111<0 fs1=19-15 vd=11-7
+vfmv.v.f common 010111100000<20|101<12|1010111<0 fs1=19-15 vd=11-7
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+mop.r.13 common 100011011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.14 common 100011011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.15 common 100011011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.16 common 110000011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.17 common 110000011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.18 common 110000011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.19 common 110000011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.2 common 100000011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.20 common 110001011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.21 common 110001011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.22 common 110001011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.23 common 110001011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.24 common 110010011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.25 common 110010011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.26 common 110010011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.27 common 110010011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.28 common 110011011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.29 common 110011011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.3 common 100000011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.30 common 110011011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.31 common 110011011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.4 common 100001011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.5 common 100001011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.6 common 100001011110<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.7 common 100001011111<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.8 common 100010011100<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.r.9 common 100010011101<20|100<12|1110011<0 xs1=19-15 xd=11-7
+mop.rr.0 common 1000001<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.1 common 1000011<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.2 common 1000101<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.3 common 1000111<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.4 common 1100001<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.5 common 1100011<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.6 common 1100101<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+mop.rr.7 common 1100111<25|100<12|1110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64ks1i 64 00110001<24|001<12|0010011<0 rnum=23-20 xs1=19-15 xd=11-7
+aes64ks2 64 0111111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes32dsi 32 10101<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes32dsmi 32 10111<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes64ds 64 0011101<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64dsm 64 0011111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64im 64 001100000000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+aes32esi 32 10001<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes32esmi 32 10011<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+aes64es 64 0011001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+aes64esm 64 0011011<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha256sig0 common 000100000010<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sig1 common 000100000011<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sum0 common 000100000000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha256sum1 common 000100000001<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig0 64 000100000110<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig0h 32 0101110<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig0l 32 0101010<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig1 64 000100000111<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sig1h 32 0101111<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sig1l 32 0101011<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sum0 64 000100000100<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sum0r 32 0101000<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sha512sum1 64 000100000101<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sha512sum1r 32 0101001<25|000<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
+sm3p0 common 000100001000<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sm3p1 common 000100001001<20|001<12|0010011<0 xs1=19-15 xd=11-7
+sm4ed common 11000<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+sm4ks common 11010<25|000<12|0110011<0 bs=31-30 xs2=24-20 xs1=19-15 xd=11-7
+vandn.vv common 000001<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vandn.vx common 000001<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vbrev.v common 010010<26|01010010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vbrev8.v common 010010<26|01000010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vclz.v common 010010<26|01100010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vcpop.v common 010010<26|01110010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vctz.v common 010010<26|01101010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vrev8.v common 010010<26|01001010<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vrol.vv common 010101<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vrol.vx common 010101<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vror.vi common 01010<27|011<12|1010111<0 imm=26|19-15 vm=25-25 vs2=24-20 vd=11-7
+vror.vv common 010100<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vror.vx common 010100<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vwsll.vi common 110101<26|011<12|1010111<0 vm=25-25 vs2=24-20 imm=19-15 vd=11-7
+vwsll.vv common 110101<26|000<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vwsll.vx common 110101<26|100<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vclmul.vv common 001100<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vclmul.vx common 001100<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vclmulh.vv common 001101<26|010<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vclmulh.vx common 001101<26|110<12|1010111<0 vm=25-25 vs2=24-20 xs1=19-15 vd=11-7
+vfncvtbf16.f.f.w common 010010<26|11101001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfwcvtbf16.f.f.v common 010010<26|01101001<12|1010111<0 vm=25-25 vs2=24-20 vd=11-7
+vfwmaccbf16.vf common 111011<26|101<12|1010111<0 vm=25-25 vs2=24-20 fs1=19-15 vd=11-7
+vfwmaccbf16.vv common 111011<26|001<12|1010111<0 vm=25-25 vs2=24-20 vs1=19-15 vd=11-7
+vghsh.vv common 1011001<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vgmul.vv common 1010001<25|10001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdf.vs common 1010011<25|00001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdf.vv common 1010001<25|00001010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdm.vs common 1010011<25|00000010<12|1110111<0 vs2=24-20 vd=11-7
+vaesdm.vv common 1010001<25|00000010<12|1110111<0 vs2=24-20 vd=11-7
+vaesef.vs common 1010011<25|00011010<12|1110111<0 vs2=24-20 vd=11-7
+vaesef.vv common 1010001<25|00011010<12|1110111<0 vs2=24-20 vd=11-7
+vaesem.vs common 1010011<25|00010010<12|1110111<0 vs2=24-20 vd=11-7
+vaesem.vv common 1010001<25|00010010<12|1110111<0 vs2=24-20 vd=11-7
+vaeskf1.vi common 1000101<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vaeskf2.vi common 1010101<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vaesz.vs common 1010011<25|00111010<12|1110111<0 vs2=24-20 vd=11-7
+vsha2ch.vv common 1011101<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsha2cl.vv common 1011111<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsha2ms.vv common 1011011<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsm3c.vi common 1010111<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vsm3me.vv common 1000001<25|010<12|1110111<0 vs2=24-20 vs1=19-15 vd=11-7
+vsm4k.vi common 1000011<25|010<12|1110111<0 vs2=24-20 imm=19-15 vd=11-7
+vsm4r.vs common 1010011<25|10000010<12|1110111<0 vs2=24-20 vd=11-7
+vsm4r.vv common 1010001<25|10000010<12|1110111<0 vs2=24-20 vd=11-7
diff --git a/arch/riscv/tools/insn_tbl.sh b/arch/riscv/tools/insn_tbl.sh
new file mode 100755
index 000000000000..0ab1e17959c4
--- /dev/null
+++ b/arch/riscv/tools/insn_tbl.sh
@@ -0,0 +1,263 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Generate riscv instruction helper header.
+# The generated helpers for each instruction are:
+#   - riscv_insn_<insn>_MASK useful to help check if arbitrary binary is <insn>
+#   - riscv_insn_<insn>_MATCH useful to help check if arbitrary binary is <insn>
+#   - riscv_insn_<insn> useful to construct <insn>
+#   - riscv_insn_<insn>_<var> useful to extract <var> from <insn>
+#
+# Each line of the instruction table should have the following format:
+#
+# NAME BASE FIXED_BITS [VARIABLE_LIST]
+#
+# NAME                        instruction name
+# BASE                        instruction base size (common[,(32|64)])
+# FIXED_BITS                  bitfields of the fixed bits of an instruction concatenated with |
+#                             each continuous grouping of fixed bits is in the format of bits<offset
+#                             all instruction variables in the form of <var>[-<sign_extend>-][<<left_shift><][!<constraint>...]
+#                             if the variable requires sign extension, surround the index to sign extend at in '-'
+#                             if the variable requires left shifting, surround the left shift amount in '<'
+#                             a "constraint" is an integer value that is invalid for this variable
+# VARIABLE_LIST               a variable sized list of all variables in the instruction definition
+#                             in the form of name[~][<num][!num...]=(high[-low])|...
+#                             symbols after the name represent different modifiers:
+#                                 ~ sign extension, can only appear once
+#                                 < left shift by 'num' amount on extraction, can only appear once
+#                                 ! mark 'num' as an invalid input for this variable, any number may appear
+#
+
+set -e
+
+usage() {
+	echo >&2 "usage: $0 BASE INFILE OUTFILE" >&2
+	echo >&2
+	echo >&2 "  INFILE    input instruction table"
+	echo >&2 "  OUTFILE   output header file"
+	exit 1
+}
+
+if [ $# -ne 2 ]; then
+	usage
+fi
+
+infile="$1"
+outfile="$2"
+
+file=$(readlink -f $0)
+
+echo "/* Auto-generated rv${base} header from script arch/${file#*arch/} */" > $outfile
+
+echo "#ifndef RISCV_INSN_GEN_H" >> $outfile
+echo "#define RISCV_INSN_GEN_H" >> $outfile
+echo >> $outfile
+
+printf "#include <linux/bits.h>" >> $outfile
+echo >> $outfile
+echo "#define COMMA ," >> $outfile
+echo "#define SEMICOLON ;" >> $outfile
+echo "#define SINGLE_ARG(...) __VA_ARGS__" >> $outfile
+echo >> $outfile
+
+grep -E "^[a-z\.0-9]+[[:space:]]+" "$infile" | {
+    while read name base fixed variables; do
+        echo "/* $name */"
+
+        compressed_name=${name##c.*}
+        invalid_inst_functions=""
+        variable_params=""
+        constraints=""
+        match=""
+        mask=""
+        make=""
+
+        # All compressed instructions start with "c."
+        size=${compressed_name:+32};
+        size=${size:-16};
+
+        # Replace all . with _
+        formatted_inst_name=$name
+        while [ ! ${formatted_inst_name##*.*} ]; do
+            prefix=${formatted_inst_name%.*}
+            suffix=${formatted_inst_name##*.}
+            contains_dot=${formatted_inst_name##*.*}
+            formatted_inst_name=${contains_dot:-${prefix}_${suffix}}
+        done
+
+        # Collect all fixed bits of an instruction
+        OLD_IFS=$IFS
+        IFS='|'
+        for segment in $fixed; do
+            bits=${segment%<*}
+            offset=${segment#*<}
+
+            len=${#bits}
+
+            mask="${mask} | 0b"
+
+            while [ $len -gt 0 ]; do
+                len=$((len - 1))
+                mask=${mask}1
+            done
+
+            if [ ${offset} -gt 0 ]; then
+                s=" << ${offset}"
+            else
+                s=""
+            fi
+
+            mask="${mask}${s}"
+
+            match="${match} | 0b${bits}${s}"
+        done
+        IFS=$OLD_IFS
+
+        # Instruction only appears in one base
+        only_base=
+        if [ "${base}" != "${base%32}" ]; then
+            echo "#if __riscv_xlen == 32"
+            only_base=32
+        elif [ "${base}" != "${base%64}" ]; then
+            echo "#if __riscv_xlen == 64"
+            only_base=64
+        fi
+
+        # Standard name for the instruction parameter in generated functions
+        insn="_insn"
+
+        for variable in ${variables}; do
+            variable_name="${variable%%[<~=!]*}"
+            parts="${variable#*=}"
+            insert_mask=""
+            sign_extend=""
+            left_shift=""
+            extract=""
+            insert=""
+
+            # Standard name for the variable parameter in generated functions
+            var="_${variable_name}"
+            variable_params="${variable_params}u32 ${var}, "
+
+            if [ "${variable}" != "${variable#*~}" ]; then
+                sign_extend="1"
+            fi
+
+            if [ "${variable}" != "${variable#*<}" ]; then
+                left_shift="${variable#*<}"
+                left_shift="${left_shift%%[=<~!]*}"
+            else
+                left_shift="0"
+            fi
+
+            if [ "${variable}" != "${variable#*!}" ]; then
+                raw_constraints="${variable#*!}"
+                raw_constraints="${raw_constraints%%[=<~!]**}"
+
+                OLD_IFS=$IFS
+                IFS='!'
+                for constraint in $raw_constraints; do
+                    constraints="${constraints}(riscv_insn_${formatted_inst_name}_extract_${variable_name}(${insn}) != ${constraint}) && "
+                done
+                IFS=$OLD_IFS
+            fi
+
+            offset=0
+            while true; do
+                part=${parts##*|}
+
+                if [ "${part#*-}" = "${part}" ]; then
+                    high="${part}"
+                    low="${part}"
+                    len=1
+                else
+                    high="${part%-*}"
+                    low="${part#*-}"
+                    len=$((high - low + 1))
+                fi
+
+                # Don't emit shift if 0
+                first_shift=${low}
+                if [ "${first_shift}" = "0" ]; then
+                    first_shift=
+                fi
+
+                second_shift=$((offset + left_shift))
+                if [ "${second_shift}" = "0" ]; then
+                    second_shift=
+                fi
+
+                extract="${extract} | ((${insn}${first_shift:+ >> }${first_shift} & GENMASK($((len - 1)), 0))${second_shift:+ << }${second_shift})"
+                insert_mask="${insert_mask} & ~GENMASK(${high}, ${low})"
+                insert="${insert} | (((${var}${second_shift:+ >> }${second_shift}) & GENMASK($((len - 1)), 0))${first_shift:+ << }${first_shift})"
+                offset=$((offset + len))
+
+                if [ "${parts}" = "${part}" ]; then
+                    # Processed all parts of variable
+                    break
+                fi
+
+                parts=${parts%|*}
+            done
+
+            extract="${extract# | }"
+
+            if [ ${sign_extend} ]; then
+                extract="sign_extend32(${extract}, ${offset})"
+                type="s"
+            else
+                type="u"
+            fi
+
+            echo "static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn})"
+            echo "{"
+            echo "\treturn ${extract};"
+            echo "}"
+            echo "static __always_inline void riscv_insn_${formatted_inst_name}_insert_${variable_name}(u${size} *${insn}, ${type}32 ${var})"
+            echo "{"
+            echo "\t*_insn &= ${insert_mask# & };"
+            echo "\t*_insn |= ${insert# | };"
+            echo "}"
+
+            if [ "${only_base}" ]; then
+                invalid_inst_functions="${invalid_inst_functions}static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn}) {\n\tpanic(\"${name} is not supported on non ${only_base}-bit systems.\");\n}\n"
+            fi
+
+            make="${make}	riscv_insn_${formatted_inst_name}_insert_${variable_name}(&${insn}, ${var});\n"
+        done
+
+        variable_params="${variable_params%, }"
+        variable_params="${variable_params:-void}"
+
+        echo "#define riscv_insn_${formatted_inst_name}_MASK (${mask# | })"
+        echo "#define riscv_insn_${formatted_inst_name}_MATCH (${match# | })"
+        echo "static __always_inline u${size} riscv_insn_${formatted_inst_name}(${variable_params})"
+        echo "{"
+        echo "\tu${size} ${insn} = riscv_insn_${formatted_inst_name}_MATCH;"
+        echo "${make}	return ${insn};"
+        echo "}"
+
+        # Check against instructions that have a variable that may contain invalid values
+        if [ "$constraints" ]; then
+            echo "__RISCV_INSN_FUNCS_CONSTRAINED(${formatted_inst_name}, ${constraints% && });"
+        else
+            echo "__RISCV_INSN_FUNCS(${formatted_inst_name});"
+        fi
+
+        # If common does not appear in the base, then this instruction only appears in one base
+        if [ "$base" = "${base#common}" ]; then
+            echo "#else"
+            echo "__RISCV_INSN_FUNCS_UNSUPPORTED(${formatted_inst_name});"
+            echo "${invalid_inst_functions%\\n}"
+        fi
+
+        # Instruction has a base variant
+        if [ "$base" != "${base%[24]}" ]; then
+            echo "#endif"
+        fi
+
+        echo
+    done
+
+    echo "#endif /* RISCV_INST_GEN_H */"
+} >> $outfile
-- 
2.52.0