Re: [PATCH v2 04/16] perf annotate-arm64: Handle load and store instructions

[Tengda Wu]

On 2026/4/7 15:09, Namhyung Kim wrote:
> On Fri, Apr 03, 2026 at 09:47:48AM +0000, Tengda Wu wrote:
>> Add ldst_ops to handle load and store instructions in order to parse
>> the data types and offsets associated with PMU events for memory access
>> instructions. There are many variants of load and store instructions in
>> ARM64, making it difficult to match all of these instruction names
>> completely. Therefore, only the instruction prefixes are matched. The
>> prefix 'ld|st' covers most of the memory access instructions, 'cas|swp'
>> matches atomic instructions, and 'prf' matches memory prefetch
>> instructions.
>>
>> Signed-off-by: Li Huafei <lihuafei1@xxxxxxxxxx>
>> Signed-off-by: Tengda Wu <wutengda@xxxxxxxxxxxxxxx>
>> ---
>>  .../perf/util/annotate-arch/annotate-arm64.c  | 72 +++++++++++++++++++
>>  1 file changed, 72 insertions(+)
>>
>> diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/util/annotate-arch/annotate-arm64.c
>> index 4c42323b0c18..8209faaa6086 100644
>> --- a/tools/perf/util/annotate-arch/annotate-arm64.c
>> +++ b/tools/perf/util/annotate-arch/annotate-arm64.c
>> @@ -3,7 +3,9 @@
>>  #include <errno.h>
>>  #include <stdlib.h>
>>  #include <string.h>
>> +#include <ctype.h>
>>  #include <linux/zalloc.h>
>> +#include <linux/string.h>
>>  #include <regex.h>
>>  #include "../annotate.h"
>>  #include "../disasm.h"
>> @@ -12,6 +14,7 @@ struct arch_arm64 {
>>  	struct arch arch;
>>  	regex_t call_insn;
>>  	regex_t jump_insn;
>> +	regex_t ldst_insn; /* load and store instruction */
>>  };
>>  
>>  static bool arm64__check_multi_regs(const char *op)
>> @@ -114,6 +117,59 @@ static const struct ins_ops arm64_mov_ops = {
>>  	.scnprintf = mov__scnprintf,
>>  };
>>  
>> +static int arm64_ldst__parse(const struct arch *arch __maybe_unused,
> 
> The 'arch' is used. :)
> 

Oh, will fix it.

> 
>> +			     struct ins_operands *ops,
>> +			     struct map_symbol *ms __maybe_unused,
>> +			     struct disasm_line *dl __maybe_unused)
>> +{
>> +	char *s, *target;
>> +
>> +	/*
>> +	 * The part starting from the memory access annotation '[' is parsed
>> +	 * as 'target', while the part before it is parsed as 'source'.
> 
> It'd be nice if you can show some examples.  So it always looks like:
> 
> 	LDR  x1, [x2, #4]
> 	STR  x1, [x3], #8
> 
> Right?  What about other instructions?
> 

Yeah. Here are some representative examples that this patch handles:

ldr     x1, [x2]
ldr     x2, [x0, #968]
ldr     w3, [x25], #4
ldp     x29, x30, [sp], #16
ldr     x0, [x1, #16]!
ldr     x6, [x23, w25, sxtw #3]

It might be better to add these examples as a block comment above
the arm64_ldst__parse().

> 
>> +	 */
>> +	target = s = strchr(ops->raw, arch->objdump.memory_ref_char);
>> +	if (!s)
>> +		return -1;
>> +
>> +	while (s > ops->raw && *s != ',')
>> +		--s;
>> +
>> +	if (s == ops->raw)
>> +		return -1;
>> +
>> +	*s = '\0';
>> +	ops->source.raw = strdup(ops->raw);
>> +
>> +	*s = ',';
>> +	if (!ops->source.raw)
>> +		return -1;
>> +
>> +	ops->source.multi_regs = arm64__check_multi_regs(ops->source.raw);
> 
> Probably it's better to set ops->source.mem_ref to false.  Then you
> won't need to set multi_regs.
> 
> Thanks,
> Namhyung

Agreed.

-- Tengda

> 
>> +
>> +	ops->target.raw = strdup(target);
>> +	if (!ops->target.raw) {
>> +		zfree(&ops->source.raw);
>> +		return -1;
>> +	}
>> +	ops->target.mem_ref = true;
>> +	ops->target.multi_regs = arm64__check_multi_regs(ops->target.raw);
>> +
>> +	return 0;
>> +}
>> +
>> +static int arm64_ldst__scnprintf(const struct ins *ins, char *bf, size_t size,
>> +				 struct ins_operands *ops, int max_ins_name)
>> +{
>> +	return scnprintf(bf, size, "%-*s %s,%s", max_ins_name, ins->name,
>> +			 ops->source.raw, ops->target.raw);
>> +}
>> +
>> +static struct ins_ops arm64_ldst_ops = {
>> +	.parse	   = arm64_ldst__parse,
>> +	.scnprintf = arm64_ldst__scnprintf,
>> +};
>> +
>>  static const struct ins_ops *arm64__associate_instruction_ops(struct arch *arch, const char *name)
>>  {
>>  	struct arch_arm64 *arm = container_of(arch, struct arch_arm64, arch);
>> @@ -124,6 +180,8 @@ static const struct ins_ops *arm64__associate_instruction_ops(struct arch *arch,
>>  		ops = &jump_ops;
>>  	else if (!regexec(&arm->call_insn, name, 2, match, 0))
>>  		ops = &call_ops;
>> +	else if (!regexec(&arm->ldst_insn, name, 2, match, 0))
>> +		ops = &arm64_ldst_ops;
>>  	else if (!strcmp(name, "ret"))
>>  		ops = &ret_ops;
>>  	else
>> @@ -148,6 +206,8 @@ const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id,
>>  	arch->id = *id;
>>  	arch->objdump.comment_char	  = '/';
>>  	arch->objdump.skip_functions_char = '+';
>> +	arch->objdump.memory_ref_char	  = '[';
>> +	arch->objdump.imm_char		  = '#';
>>  	arch->associate_instruction_ops   = arm64__associate_instruction_ops;
>>  
>>  	/* bl, blr */
>> @@ -161,8 +221,20 @@ const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id,
>>  	if (err)
>>  		goto out_free_call;
>>  
>> +	/*
>> +	 * The ARM64 architecture has many variants of load/store instructions.
>> +	 * It is quite challenging to match all of them completely. Here, we
>> +	 * only match the prefixes of these instructions.
>> +	 */
>> +	err = regcomp(&arm->ldst_insn, "^(ld|st|cas|prf|swp)",
>> +		      REG_EXTENDED);
>> +	if (err)
>> +		goto out_free_jump;
>> +
>>  	return arch;
>>  
>> +out_free_jump:
>> +	regfree(&arm->jump_insn);
>>  out_free_call:
>>  	regfree(&arm->call_insn);
>>  out_free_arm:
>> -- 
>> 2.34.1
>>