Re: [PATCH v3] dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints

[Krzysztof Kozlowski]

On Fri, Apr 10, 2026 at 04:29:55PM +0530, Swamil Jain wrote:
>    clocks:
> +    minItems: 2
>      items:
>        - description: fck DSS functional clock
>        - description: vp1 Video Port 1 pixel clock
>        - description: vp2 Video Port 2 pixel clock
>  
>    clock-names:
> +    minItems: 2
>      items:
>        - const: fck
>        - const: vp1
> @@ -179,6 +195,20 @@ allOf:
>          ports:
>            properties:
>              port@1: false
> +        clock-names:
> +          maxItems: 2
> +        clocks:
> +          maxItems: 2
> +        reg:
> +          maxItems: 5

Also constrain for reg-names,

> +    else:
> +      properties:
> +        clock-names:
> +          minItems: 3
> +        clocks:
> +          minItems: 3
> +        reg:
> +          minItems: 8

Same here, please.

And if you are sending new version: they should be listed in the same
order as in top-level properties, so reg, reg-names, clocks and
clock-names. (juging by the diff)

Best regards,
Krzysztof