Re: [PATCH v3] net/mlx5: Fix OOB access and stack information leak in PTP event handling

[prathamesh deshpande]

Hi Carolina,

Thanks for the feedback. I have just submitted v4 which addresses this
by checking the pin index against MAX_PIN_NUM.

Thanks,
Prathamesh


On Sat, Apr 11, 2026 at 12:35 PM Carolina Jubran <cjubran@xxxxxxxxxx> wrote:
>
>
> On 10/04/2026 4:53, Prathamesh Deshpande wrote:
> > In mlx5_pps_event(), several critical issues were identified during
> > review by Sashiko:
> >
> > 1. The 'pin' index from the hardware event was used without bounds
> >     checking to index 'pin_config' and 'pps_info->start', leading to
> >     potential out-of-bounds memory access.
> > 2. 'ptp_event' was not zero-initialized. Since it contains a union,
> >     assigning a timestamp partially leaves the 'ts_raw' field with
> >     uninitialized stack memory, which can leak kernel data or
> >     corrupt time sync logic in hardpps().
> > 3. A NULL 'pin_config' could be dereferenced if initialization failed.
> > 4. 'clock->ptp' could be NULL if ptp_clock_register() failed.
> >
> > Fix these by zero-initializing the event struct, adding a bounds
> > check against n_pins, and adding appropriate NULL guards.
> >
> > Fixes: 7c39afb394c7 ("net/mlx5: PTP code migration to driver core section")
> > Suggested-by: Carolina Jubran <cjubran@xxxxxxxxxx>
> > Signed-off-by: Prathamesh Deshpande <prathameshdeshpande7@xxxxxxxxx>
> > ---
> > v3:
> > - Fix union corruption by using a local timestamp variable [Sashiko].
> > - Validate pin index against n_pins with WARN_ON_ONCE [Carolina].
> > - Remove redundant pin < 0 check and cleanup TODO comment.
> > v2:
> > - Zero-initialize ptp_event to prevent stack information leak [Sashiko].
> > - Add bounds check for hardware pin index to prevent OOB access [Sashiko].
> > - Add NULL guard for pin_config to handle initialization failures [Sashiko].
> > - Add NULL check for clock->ptp as originally intended.
> >
> >   .../net/ethernet/mellanox/mlx5/core/lib/clock.c | 17 ++++++++++++-----
> >   1 file changed, 12 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > index bd4e042077af..674dd048a6b8 100644
> > --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
> > @@ -1164,16 +1164,22 @@ static int mlx5_pps_event(struct notifier_block *nb,
> >                                                              pps_nb);
> >       struct mlx5_core_dev *mdev = clock_state->mdev;
> >       struct mlx5_clock *clock = mdev->clock;
> > -     struct ptp_clock_event ptp_event;
> > +     struct ptp_clock_event ptp_event = {};
> >       struct mlx5_eqe *eqe = data;
> >       int pin = eqe->data.pps.pin;
> >       unsigned long flags;
> >       u64 ns;
> >
> > +     if (!clock->ptp_info.pin_config)
> > +             return NOTIFY_OK;
> > +
> > +     if (WARN_ON_ONCE(pin >= clock->ptp_info.n_pins))
> > +             return NOTIFY_OK;
>
>
> Sorry if my previous comment wasn't clear enough.
>
>
> The firmware will never report a pin higher than n_pins, thats not the
> concern
>
> here. if future hardware reports n_pins > 8, checking against n_pins
> would still
>
> allow OOB access on those arrays. The check should compare against
> MAX_PIN_NUM
>
> instead, since thats the actual hard limit of the driver's data
> structures. and if a new
>
> device supports more than 8 pins, the WARN_ON_ONCE would let us know we need
>
> to update the driver.
>
>
> Thanks,
>
> Carolina
>


-- 
Thanks and Regards,
Prathamesh Deshpande