Re: [PATCH v2 4/5] LoongArch: BPF: Support load-acquire and store-release instructions

[Tiezhu Yang]

On 2026/4/12 上午11:46, WANG Rui wrote:
> On Tue, Apr 7, 2026 at 2:23 PM Tiezhu Yang <yangtiezhu@xxxxxxxxxxx> wrote:
> > Use the LoongArch common memory access instructions with the barrier dbar
> > to support the BPF load-acquire and store-release instructions.

...
> > +static int emit_atomic_ld_st(const struct bpf_insn *insn, struct jit_ctx *ctx)
> > +{
> > +       const u8 t1 = LOONGARCH_GPR_T1;
> > +       const u8 src = regmap[insn->src_reg];
> > +       const u8 dst = regmap[insn->dst_reg];
> > +       const s16 off = insn->off;
> > +       const s32 imm = insn->imm;
> > +
> > +       switch (imm) {
> > +       /* dst_reg = load_acquire(src_reg + off16) */
> > +       case BPF_LOAD_ACQ:
> > +               switch (BPF_SIZE(insn->code)) {
> > +               case BPF_B:
> > +                       if (is_signed_imm12(off)) {
> > +                               emit_insn(ctx, ldb, dst, src, off);
> > +                       } else {
> > +                               move_imm(ctx, t1, off, false);
> > +                               emit_insn(ctx, ldxb, dst, src, t1);
> > +                       }
> > +                       emit_zext_8(ctx, dst);
>
> Could we use ld[x].{bu,hu,wu} here to simplify this?

Yes, this is better, the instructions are zero extended, so no need
to use the bstrinsd instruction to clear the higher bits explicitly,
thanks for your suggestion.

I tested the changes, it works well, v3 is coming soon.

Thanks,
Tiezhu