Re: [PATCH V4] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

[Arnd Bergmann]

On Sun, Apr 12, 2026, at 16:31, guoren@xxxxxxxxxx wrote:
>  arch/riscv/Kconfig.errata                    | 17 ++++++++++
>  arch/riscv/errata/thead/errata.c             | 20 ++++++++++++
>  arch/riscv/include/asm/errata_list_vendors.h |  3 +-
>  arch/riscv/include/asm/rwonce.h              | 34 ++++++++++++++++++++
>  include/asm-generic/rwonce.h                 |  2 ++

For asm-generic:

Acked-by: Arnd Bergmann <arnd@xxxxxxxx>

> +static bool errata_probe_write_once(unsigned int stage,
> +				    unsigned long arch_id, unsigned long impid)
> +{
> +	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE))
> +		return false;
> +
> +	/* target-c9xx cores report arch_id and impid as 0 */
> +	if (arch_id != 0 || impid != 0)
> +		return false;
> +
> +	if (stage == RISCV_ALTERNATIVES_BOOT ||
> +	    stage == RISCV_ALTERNATIVES_MODULE)
> +		return true;

Question: Are the affected cores the only ones that report
arch_id==impid==0? If there are other known implementations
that get the extra barrier but don't need it here, that
should probably be mentioned in the Kconfig text and
the code comment.

      Arnd