Re: [PATCH 01/11] dt-bindings: media: qcom,glymur-iris: Add glymur video codec

[Vishnu Reddy]

On 4/14/2026 12:55 PM, Krzysztof Kozlowski wrote:
> On Tue, Apr 14, 2026 at 10:29:57AM +0530, Vishnu Reddy wrote:
> > Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
> > is a new generation of video IP that introduces a dual-core architecture.
> > The second core brings its own power domain, clocks, and reset lines,
> > requiring additional power domains and clocks in the power sequence.
> >
> > Signed-off-by: Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
> > ---
> >   .../bindings/media/qcom,glymur-iris.yaml           | 220 +++++++++++++++++++++
> >   include/dt-bindings/media/qcom,glymur-iris.h       |  11 ++
> >   2 files changed, 231 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
> > new file mode 100644
> > index 000000000000..10ee02cd1a7d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
> > @@ -0,0 +1,220 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Glymur SoC Iris video encoder and decoder
> > +
> > +maintainers:
> > +  - Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
> > +
> > +description:
> > +  The Iris video processing unit on Qualcomm Glymur SoC is a video encode and
> > +  decode accelerator.
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,glymur-iris
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 9
> > +
> > +  clock-names:
> > +    items:
> > +      - const: iface
> > +      - const: core
> > +      - const: vcodec0_core
> iface1 goes here
> core_freerun
> vcodec0_core_freerun
> and the rest, based on sm8750. Or which previous variant did you use as
> the base?
Ack, will use sm8750 as base and I'll update.
Thanks for the suggestion.
> > +      - const: iface_ctrl
> > +      - const: core_freerun
> > +      - const: vcodec0_core_freerun
> > +      - const: iface1
> > +      - const: vcodec1_core
> > +      - const: vcodec1_core_freerun
> > +
> > +  dma-coherent: true
> > +
> > +  firmware-name:
> > +    maxItems: 1
> > +
> > +  interconnects:
> > +    maxItems: 2
> > +
> > +  interconnect-names:
> > +    items:
> > +      - const: cpu-cfg
> > +      - const: video-mem
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  iommus:
> > +    maxItems: 4
> > +
> > +  iommu-map:
> > +    maxItems: 1
> > +
> > +  memory-region:
> > +    maxItems: 1
> > +
> > +  operating-points-v2: true
> > +  opp-table:
> > +    type: object
> > +
> > +  power-domains:
> > +    maxItems: 5
> > +
> > +  power-domain-names:
> > +    items:
> > +      - const: venus
> > +      - const: vcodec0
> > +      - const: mxc
> > +      - const: mmcx
> > +      - const: vcodec1
> > +
> > +  resets:
> > +    maxItems: 6
> > +
> > +  reset-names:
> > +    items:
> > +      - const: bus0
> bus1
> core
> vcodec0_core
Ack
> > +      - const: bus_ctrl
>
> > +      - const: core
> > +      - const: vcodec0_core
> > +      - const: bus1
> > +      - const: vcodec1_core
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - dma-coherent
> > +  - interconnects
> > +  - interconnect-names
> > +  - interrupts
> > +  - iommus
> > +  - memory-region
> > +  - power-domains
> > +  - power-domain-names
> > +  - resets
> > +  - reset-names
> > +
> > +unevaluatedProperties: false
> Use existing, most recent code as starting point.
Ack, will use sm8750.
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/media/qcom,glymur-iris.h>
> > +    #include <dt-bindings/power/qcom,rpmhpd.h>
> > +
> > +    video-codec@aa00000 {
> > +        compatible = "qcom,glymur-iris";
> > +        reg = <0x0aa00000 0xf0000>;
> > +
> > +        clocks = <&gcc_video_axi0_clk>,
> > +                 <&videocc_mvs0c_clk>,
> > +                 <&videocc_mvs0_clk>,
> > +                 <&gcc_video_axi0c_clk>,
> > +                 <&videocc_mvs0c_freerun_clk>,
> > +                 <&videocc_mvs0_freerun_clk>,
> > +                 <&gcc_video_axi1_clk>,
> > +                 <&videocc_mvs1_clk>,
> > +                 <&videocc_mvs1_freerun_clk>;
> > +        clock-names = "iface",
> > +                      "core",
> > +                      "vcodec0_core",
> > +                      "iface_ctrl",
> > +                      "core_freerun",
> > +                      "vcodec0_core_freerun",
> > +                      "iface1",
> > +                      "vcodec1_core",
> > +                      "vcodec1_core_freerun";
> > +
> > +        dma-coherent;
> > +
> > +        interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>,
> > +                        <&mmss_noc_master_video &mc_virt_slave_ebi1>;
> > +        interconnect-names = "cpu-cfg",
> > +                             "video-mem";
> > +
> > +        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +        iommus = <&apps_smmu 0x1940 0x0>,
> > +                 <&apps_smmu 0x1943 0x0>,
> > +                 <&apps_smmu 0x1944 0x0>,
> > +                 <&apps_smmu 0x19e0 0x0>;
> > +
> > +        iommu-map = <IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;
> > +
> > +        memory-region = <&video_mem>;
> > +
> > +        operating-points-v2 = <&iris_opp_table>;
> > +
> > +        power-domains = <&videocc_mvs0c_gdsc>,
> > +                        <&videocc_mvs0_gdsc>,
> > +                        <&rpmhpd RPMHPD_MXC>,
> > +                        <&rpmhpd RPMHPD_MMCX>,
> > +                        <&videocc_mvs1_gdsc>;
> > +        power-domain-names = "venus",
> > +                             "vcodec0",
> > +                             "mxc",
> > +                             "mmcx",
> > +                             "vcodec1";
> > +
> > +        resets = <&gcc_video_axi0_clk_ares>,
> > +                 <&gcc_video_axi0c_clk_ares>,
> > +                 <&videocc_mvs0c_freerun_clk_ares>,
> > +                 <&videocc_mvs0_freerun_clk_ares>,
> > +                 <&gcc_video_axi1_clk_ares>,
> > +                 <&videocc_mvs1_freerun_clk_ares>;
> > +        reset-names = "bus0",
> > +                      "bus_ctrl",
> > +                      "core",
> > +                      "vcodec0_core",
> > +                      "bus1",
> > +                      "vcodec1_core";
> > +
> > +        iris_opp_table: opp-table {
> > +            compatible = "operating-points-v2";
> > +
> > +            opp-240000000 {
> > +                opp-hz = /bits/ 64 <240000000 240000000 360000000>;
> > +                required-opps = <&rpmhpd_opp_svs>,
> > +                                <&rpmhpd_opp_low_svs>;
> > +            };
> > +
> > +            opp-338000000 {
> > +                opp-hz = /bits/ 64 <338000000 338000000 507000000>;
> > +                required-opps = <&rpmhpd_opp_svs>,
> > +                                <&rpmhpd_opp_svs>;
> > +            };
> > +
> > +            opp-366000000 {
> > +                opp-hz = /bits/ 64 <366000000 366000000 549000000>;
> > +                required-opps = <&rpmhpd_opp_svs_l1>,
> > +                                <&rpmhpd_opp_svs_l1>;
> > +            };
> > +
> > +            opp-444000000 {
> > +                opp-hz = /bits/ 64 <444000000 444000000 666000000>;
> > +                required-opps = <&rpmhpd_opp_svs_l1>,
> > +                                <&rpmhpd_opp_nom>;
> > +            };
> > +
> > +            opp-533333334 {
> > +                opp-hz = /bits/ 64 <533333334 533333334 800000000>;
> > +                required-opps = <&rpmhpd_opp_svs_l1>,
> > +                                <&rpmhpd_opp_turbo>;
> > +            };
> > +
> > +            opp-655000000 {
> > +                opp-hz = /bits/ 64 <655000000 655000000 982000000>;
> > +                required-opps = <&rpmhpd_opp_nom>,
> > +                                <&rpmhpd_opp_turbo_l1>;
> > +            };
> > +        };
> > +    };
> > diff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bindings/media/qcom,glymur-iris.h
> > new file mode 100644
> > index 000000000000..5766db0b9247
> > --- /dev/null
> > +++ b/include/dt-bindings/media/qcom,glymur-iris.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
> > +#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
> > +
> > +#define IRIS_FIRMWARE	0
> For what is this define? IOMMU map? Binding is quiet about it, so
> probably this should have some prefix to make it obvious.
> IOMMU_? DEV_? What does this define express?

It's a function ID. I'll add prefix like this IOMMU_FID_IRIS_FIRMWARE.

Thanks,
Vishnu Reddy

> Best regards,
> Krzysztof