RE: [PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info

[Biju Das]

Hi,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 20 April 2026 11:43
> Subject: [PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.
> Add prescale_mult variable to struct rzg2l_gpt_info for handling this difference.
> 
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v4->v5:
>  * No change.
> v3->v4:
>  * Updated commit header and description
>  * Renamed prescale_pow_of_two_mult_factor->prescale_mult
> v2->v3:
>  * No change.
> v1->v2:
>  * Collected tag.
> ---
>  drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index af594c1ce536..4324ffc8629d
> 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -92,6 +92,7 @@
> 
>  struct rzg2l_gpt_info {
>  	u32 gtcr_tpcs;
> +	u8 prescale_mult;
>  };
> 
>  struct rzg2l_gpt_chip {
> @@ -234,6 +235,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,  static u64
> rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
>  					      u32 val, u8 prescale)
>  {
> +	const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
>  	u64 tmp;
> 
>  	/*
> @@ -243,15 +245,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
>  	 *     < 2^32 * 2^10 * 2^20
>  	 *     = 2^62
>  	 */
> -	tmp = (u64)val << (2 * prescale);
> +	tmp = (u64)val << (info->prescale_mult * prescale);
>  	tmp *= USEC_PER_SEC;
> 
>  	return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);  }
> 
> -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
> +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,
> +					u64 period_or_duty_cycle, u8 prescale)
>  {
> -	return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
> +	return min_t(u64,
> +		     DIV_ROUND_DOWN_ULL(period_or_duty_cycle,
> +					1 << (info->prescale_mult * prescale)),
>  		     U32_MAX);
>  }
> 
> @@ -262,6 +267,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
> 
>  {
>  	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
> +	const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
>  	struct rzg2l_gpt_waveform *wfhw = _wfhw;
>  	bool is_small_second_period = false;
>  	u8 ch = RZG2L_GET_CH(pwm->hwpwm);
> @@ -299,8 +305,8 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
>  		}
>  	}
> 
> -	wfhw->prescale = rzg2l_gpt_calculate_prescale(period_ticks);
> -	pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
> +	wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);

This is wrong here, as I dropped rzg2l_gpt in patch #3.


Cheers,
Biju