[PATCH 04/13] drm/msm/registers: Add perfcntr json

From: Rob Clark

Date: Mon Apr 20 2026 - 18:27:46 EST

Pull in perfcntr json and wire up generation of perfcntr tables.

Sync from https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40522

Signed-off-by: Rob Clark <robin.clark@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/Makefile | 17 ++
.../msm/registers/adreno/a6xx_perfcntrs.json | 105 ++++++++
.../msm/registers/adreno/a7xx_perfcntrs.json | 228 +++++++++++++++++
.../msm/registers/adreno/a8xx_perfcntrs.json | 240 ++++++++++++++++++
4 files changed, 590 insertions(+)
create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index ce00cfb0a875..55388544de9f 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -176,6 +176,11 @@ quiet_cmd_headergen = GENHDR $@
cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
$(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@

+# TODO how to do this for a2xx/a5xx which have different .xml arg?
+quiet_cmd_headergen_json = GENHDRJSN $@
+ cmd_headergen_json = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
+ $(headergen-opts) --rnn $(src)/registers --xml $(src)/registers/adreno/a6xx.xml perfcntrs --json $< > $@
+
$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
$(src)/registers/adreno/adreno_common.xml \
$(src)/registers/adreno/adreno_pm4.xml \
@@ -192,6 +197,18 @@ $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
FORCE
$(call if_changed,headergen)

+$(obj)/generated/%.json.c: $(src)/registers/adreno/%.json \
+ $(src)/registers/adreno/a6xx_perfcntrs.json \
+ $(src)/registers/adreno/a7xx_perfcntrs.json \
+ $(src)/registers/adreno/a8xx_perfcntrs.json \
+ FORCE
+ $(call if_changed,headergen_json)
+
+adreno-y += \
+ generated/a6xx_perfcntrs.json.o \
+ generated/a7xx_perfcntrs.json.o \
+ generated/a8xx_perfcntrs.json.o \
+
ADRENO_HEADERS = \
generated/a2xx.xml.h \
generated/a3xx.xml.h \
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
new file mode 100644
index 000000000000..8bb31820479e
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
@@ -0,0 +1,105 @@
+{
+ "chip": "A6XX",
+ "groups": [
+ {
+ "name": "CP",
+ "num": 14,
+ "reserved": [ 0 ],
+ "select": "CP_PERFCTR_CP_SEL",
+ "counter": "RBBM_PERFCTR_CP",
+ "countable_type": "a6xx_cp_perfcounter_select"
+ },
+ {
+ "name": "CCU",
+ "num": 5,
+ "select": "RB_PERFCTR_CCU_SEL",
+ "counter": "RBBM_PERFCTR_CCU",
+ "countable_type": "a6xx_ccu_perfcounter_select"
+ },
+ {
+ "name": "TSE",
+ "num": 4,
+ "select": "GRAS_PERFCTR_TSE_SEL",
+ "counter": "RBBM_PERFCTR_TSE",
+ "countable_type": "a6xx_tse_perfcounter_select"
+ },
+ {
+ "name": "RAS",
+ "num": 4,
+ "select": "GRAS_PERFCTR_RAS_SEL",
+ "counter": "RBBM_PERFCTR_RAS",
+ "countable_type": "a6xx_ras_perfcounter_select"
+ },
+ {
+ "name": "LRZ",
+ "num": 4,
+ "select": "GRAS_PERFCTR_LRZ_SEL",
+ "counter": "RBBM_PERFCTR_LRZ",
+ "countable_type": "a6xx_lrz_perfcounter_select"
+ },
+ {
+ "name": "HLSQ",
+ "num": 6,
+ "select": "HLSQ_PERFCTR_HLSQ_SEL",
+ "counter": "RBBM_PERFCTR_HLSQ",
+ "countable_type": "a6xx_hlsq_perfcounter_select"
+ },
+ {
+ "name": "PC",
+ "num": 8,
+ "select": "PC_PERFCTR_PC_SEL",
+ "counter": "RBBM_PERFCTR_PC",
+ "countable_type": "a6xx_pc_perfcounter_select"
+ },
+ {
+ "name": "RB",
+ "num": 8,
+ "select": "RB_PERFCTR_RB_SEL",
+ "counter": "RBBM_PERFCTR_RB",
+ "countable_type": "a6xx_rb_perfcounter_select"
+ },
+ {
+ "name": "SP",
+ "num": 24,
+ "reserved": [ 0 ],
+ "select": "SP_PERFCTR_SP_SEL",
+ "counter": "RBBM_PERFCTR_SP",
+ "countable_type": "a6xx_sp_perfcounter_select"
+ },
+ {
+ "name": "TP",
+ "num": 12,
+ "select": "TPL1_PERFCTR_TP_SEL",
+ "counter": "RBBM_PERFCTR_TP",
+ "countable_type": "a6xx_tp_perfcounter_select"
+ },
+ {
+ "name": "UCHE",
+ "num": 12,
+ "select": "UCHE_PERFCTR_UCHE_SEL",
+ "counter": "RBBM_PERFCTR_UCHE",
+ "countable_type": "a6xx_uche_perfcounter_select"
+ },
+ {
+ "name": "VFD",
+ "num": 8,
+ "select": "VFD_PERFCTR_VFD_SEL",
+ "counter": "RBBM_PERFCTR_VFD",
+ "countable_type": "a6xx_vfd_perfcounter_select"
+ },
+ {
+ "name": "VPC",
+ "num": 6,
+ "select": "VPC_PERFCTR_VPC_SEL",
+ "counter": "RBBM_PERFCTR_VPC",
+ "countable_type": "a6xx_vpc_perfcounter_select"
+ },
+ {
+ "name": "VSC",
+ "num": 2,
+ "select": "VSC_PERFCTR_VSC_SEL",
+ "counter": "RBBM_PERFCTR_VSC",
+ "countable_type": "a6xx_vsc_perfcounter_select"
+ }
+ ]
+}
diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
new file mode 100644
index 000000000000..e60aab1862ec
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
@@ -0,0 +1,228 @@
+{
+ "chip": "A7XX",
+ "groups": [
+ {
+ "name": "CP",
+ "num": 14,
+ "reserved": [ 0 ],
+ "select": "CP_PERFCTR_CP_SEL",
+ "counter": "RBBM_PERFCTR_CP",
+ "countable_type": "a7xx_cp_perfcounter_select"
+ },
+ {
+ "name": "RBBM",
+ "num": 4,
+ "select": "RBBM_PERFCTR_RBBM_SEL",
+ "counter": "RBBM_PERFCTR_RBBM",
+ "countable_type": "a7xx_rbbm_perfcounter_select"
+ },
+ {
+ "name": "PC",
+ "pipe": "BR",
+ "num": 8,
+ "select": "PC_PERFCTR_PC_SEL",
+ "counter": "RBBM_PERFCTR_PC",
+ "countable_type": "a7xx_pc_perfcounter_select"
+ },
+ {
+ "name": "VFD",
+ "pipe": "BR",
+ "num": 8,
+ "select": "VFD_PERFCTR_VFD_SEL",
+ "counter": "RBBM_PERFCTR_VFD",
+ "countable_type": "a7xx_vfd_perfcounter_select"
+ },
+ {
+ "name": "HLSQ",
+ "pipe": "BR",
+ "num": 6,
+ "select": "SP_PERFCTR_HLSQ_SEL",
+ "counter": "RBBM_PERFCTR_HLSQ",
+ "countable_type": "a7xx_hlsq_perfcounter_select"
+ },
+ {
+ "name": "VPC",
+ "pipe": "BR",
+ "num": 6,
+ "select": "VPC_PERFCTR_VPC_SEL",
+ "counter": "RBBM_PERFCTR_VPC",
+ "countable_type": "a7xx_vpc_perfcounter_select"
+ },
+ {
+ "name": "TSE",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_TSE_SEL",
+ "counter": "RBBM_PERFCTR_TSE",
+ "countable_type": "a7xx_tse_perfcounter_select"
+ },
+ {
+ "name": "RAS",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_RAS_SEL",
+ "counter": "RBBM_PERFCTR_RAS",
+ "countable_type": "a7xx_ras_perfcounter_select"
+ },
+ {
+ "name": "UCHE",
+ "num": 12,
+ "select": "UCHE_PERFCTR_UCHE_SEL",
+ "counter": "RBBM_PERFCTR_UCHE",
+ "countable_type": "a7xx_uche_perfcounter_select"
+ },
+ {
+ "name": "TP",
+ "pipe": "BR",
+ "num": 12,
+ "select": "TPL1_PERFCTR_TP_SEL",
+ "counter": "RBBM_PERFCTR_TP",
+ "countable_type": "a7xx_tp_perfcounter_select"
+ },
+ {
+ "name": "SP",
+ "pipe": "BR",
+ "num": 24,
+ "select": "SP_PERFCTR_SP_SEL",
+ "counter": "RBBM_PERFCTR_SP",
+ "countable_type": "a7xx_sp_perfcounter_select"
+ },
+ {
+ "name": "RB",
+ "num": 8,
+ "select": "RB_PERFCTR_RB_SEL",
+ "counter": "RBBM_PERFCTR_RB",
+ "countable_type": "a7xx_rb_perfcounter_select"
+ },
+ {
+ "name": "VSC",
+ "num": 2,
+ "select": "VSC_PERFCTR_VSC_SEL",
+ "counter": "RBBM_PERFCTR_VSC",
+ "countable_type": "a7xx_vsc_perfcounter_select"
+ },
+ {
+ "name": "CCU",
+ "num": 5,
+ "select": "RB_PERFCTR_CCU_SEL",
+ "counter": "RBBM_PERFCTR_CCU",
+ "countable_type": "a7xx_ccu_perfcounter_select"
+ },
+ {
+ "name": "LRZ",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_LRZ_SEL",
+ "counter": "RBBM_PERFCTR_LRZ",
+ "countable_type": "a7xx_lrz_perfcounter_select"
+ },
+ {
+ "name": "CMP",
+ "num": 4,
+ "select": "RB_PERFCTR_CMP_SEL",
+ "counter": "RBBM_PERFCTR_CMP",
+ "countable_type": "a7xx_cmp_perfcounter_select"
+ },
+ {
+ "name": "UFC",
+ "pipe": "BR",
+ "num": 4,
+ "select": "RB_PERFCTR_UFC_SEL",
+ "counter": "RBBM_PERFCTR_UFC",
+ "countable_type": "a7xx_ufc_perfcounter_select"
+ },
+ {
+ "name": "BV_CP",
+ "num": 7,
+ "select": "CP_BV_PERFCTR_CP_SEL",
+ "counter": "RBBM_PERFCTR2_CP",
+ "countable_type": "a7xx_cp_perfcounter_select"
+ },
+ {
+ "name": "BV_PC",
+ "pipe": "BV",
+ "num": 8,
+ "select_offset": 8,
+ "select": "PC_PERFCTR_PC_SEL",
+ "counter": "RBBM_PERFCTR_BV_PC",
+ "countable_type": "a7xx_pc_perfcounter_select"
+ },
+ {
+ "name": "BV_VFD",
+ "pipe": "BV",
+ "num": 8,
+ "select_offset": 8,
+ "select": "VFD_PERFCTR_VFD_SEL",
+ "counter": "RBBM_PERFCTR_BV_VFD",
+ "countable_type": "a7xx_vfd_perfcounter_select"
+ },
+ {
+ "name": "BV_VPC",
+ "pipe": "BV",
+ "num": 6,
+ "select_offset": 6,
+ "select": "VPC_PERFCTR_VPC_SEL",
+ "counter": "RBBM_PERFCTR_BV_VPC",
+ "countable_type": "a7xx_vpc_perfcounter_select"
+ },
+ {
+ "name": "BV_TP",
+ "pipe": "BV",
+ "num": 6,
+ "select_offset": 12,
+ "select": "TPL1_PERFCTR_TP_SEL",
+ "counter": "RBBM_PERFCTR2_TP",
+ "countable_type": "a7xx_tp_perfcounter_select"
+ },
+ {
+ "name": "BV_SP",
+ "pipe": "BV",
+ "num": 12,
+ "select_offset": 24,
+ "select": "SP_PERFCTR_SP_SEL",
+ "counter": "RBBM_PERFCTR2_SP",
+ "countable_type": "a7xx_sp_perfcounter_select"
+ },
+ {
+ "name": "BV_UFC",
+ "pipe": "BV",
+ "num": 2,
+ "select_offset": 4,
+ "select": "RB_PERFCTR_UFC_SEL",
+ "counter": "RBBM_PERFCTR2_UFC",
+ "countable_type": "a7xx_ufc_perfcounter_select"
+ },
+ {
+ "name": "BV_TSE",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_TSE_SEL",
+ "counter": "RBBM_PERFCTR_BV_TSE",
+ "countable_type": "a7xx_tse_perfcounter_select"
+ },
+ {
+ "name": "BV_RAS",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_RAS_SEL",
+ "counter": "RBBM_PERFCTR_BV_RAS",
+ "countable_type": "a7xx_ras_perfcounter_select"
+ },
+ {
+ "name": "BV_LRZ",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_LRZ_SEL",
+ "counter": "RBBM_PERFCTR_BV_LRZ",
+ "countable_type": "a7xx_lrz_perfcounter_select"
+ },
+ {
+ "name": "BV_HLSQ",
+ "pipe": "BV",
+ "num": 6,
+ "select": "SP_PERFCTR_HLSQ_SEL",
+ "counter": "RBBM_PERFCTR2_HLSQ",
+ "countable_type": "a7xx_hlsq_perfcounter_select"
+ }
+ ]
+}
diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
new file mode 100644
index 000000000000..503b113df397
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
@@ -0,0 +1,240 @@
+{
+ "chip": "A8XX",
+ "groups": [
+ {
+ "name": "CP",
+ "num": 14,
+ "reserved": [ 0 ],
+ "select": "CP_PERFCTR_CP_SEL",
+ "counter": "RBBM_PERFCTR_CP",
+ "countable_type": "a8xx_cp_perfcounter_select"
+ },
+ {
+ "name": "RBBM",
+ "num": 4,
+ "select": "RBBM_PERFCTR_RBBM_SEL",
+ "slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ],
+ "counter": "RBBM_PERFCTR_RBBM",
+ "countable_type": "a8xx_rbbm_perfcounter_select"
+ },
+ {
+ "name": "PC",
+ "pipe": "BR",
+ "num": 8,
+ "select": "PC_PERFCTR_PC_SEL",
+ "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
+ "counter": "RBBM_PERFCTR_PC",
+ "countable_type": "a8xx_pc_perfcounter_select"
+ },
+ {
+ "name": "VFD",
+ "pipe": "BR",
+ "num": 8,
+ "select": "VFD_PERFCTR_VFD_SEL",
+ "counter": "RBBM_PERFCTR_VFD",
+ "countable_type": "a8xx_vfd_perfcounter_select"
+ },
+ {
+ "name": "HLSQ",
+ "pipe": "BR",
+ "num": 6,
+ "select": "SP_PERFCTR_HLSQ_SEL",
+ "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
+ "counter": "RBBM_PERFCTR_HLSQ",
+ "countable_type": "a8xx_hlsq_perfcounter_select"
+ },
+ {
+ "name": "VPC",
+ "pipe": "BR",
+ "num": 6,
+ "select": "VPC_PERFCTR_VPC_SEL",
+ "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
+ "counter": "RBBM_PERFCTR_VPC",
+ "countable_type": "a8xx_vpc_perfcounter_select"
+ },
+ {
+ "name": "TSE",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_TSE_SEL",
+ "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
+ "counter": "RBBM_PERFCTR_TSE",
+ "countable_type": "a8xx_tse_perfcounter_select"
+ },
+ {
+ "name": "RAS",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_RAS_SEL",
+ "counter": "RBBM_PERFCTR_RAS",
+ "countable_type": "a8xx_ras_perfcounter_select"
+ },
+ {
+ "name": "UCHE",
+ "num": 12,
+ "select": "UCHE_PERFCTR_UCHE_SEL",
+ "counter": "RBBM_PERFCTR_UCHE",
+ "countable_type": "a8xx_uche_perfcounter_select"
+ },
+ {
+ "name": "TP",
+ "pipe": "BR",
+ "num": 12,
+ "select": "TPL1_PERFCTR_TP_SEL",
+ "counter": "RBBM_PERFCTR_TP",
+ "countable_type": "a8xx_tp_perfcounter_select"
+ },
+ {
+ "name": "SP",
+ "pipe": "BR",
+ "num": 24,
+ "select": "SP_PERFCTR_SP_SEL",
+ "counter": "RBBM_PERFCTR_SP",
+ "countable_type": "a8xx_sp_perfcounter_select"
+ },
+ {
+ "name": "RB",
+ "pipe": "BR",
+ "num": 8,
+ "select": "RB_PERFCTR_RB_SEL",
+ "counter": "RBBM_PERFCTR_RB",
+ "countable_type": "a8xx_rb_perfcounter_select"
+ },
+ {
+ "name": "VSC",
+ "num": 2,
+ "select": "VSC_PERFCTR_VSC_SEL",
+ "counter": "RBBM_PERFCTR_VSC",
+ "countable_type": "a8xx_vsc_perfcounter_select"
+ },
+ {
+ "name": "CCU",
+ "pipe": "BR",
+ "num": 5,
+ "select": "RB_PERFCTR_CCU_SEL",
+ "counter": "RBBM_PERFCTR_CCU",
+ "countable_type": "a8xx_ccu_perfcounter_select"
+ },
+ {
+ "name": "LRZ",
+ "pipe": "BR",
+ "num": 4,
+ "select": "GRAS_PERFCTR_LRZ_SEL",
+ "counter": "RBBM_PERFCTR_LRZ",
+ "countable_type": "a8xx_lrz_perfcounter_select"
+ },
+ {
+ "name": "CMP",
+ "num": 4,
+ "select": "RB_PERFCTR_CMP_SEL",
+ "counter": "RBBM_PERFCTR_CMP",
+ "countable_type": "a8xx_cmp_perfcounter_select"
+ },
+ {
+ "name": "UFC",
+ "pipe": "BR",
+ "num": 4,
+ "select": "RB_PERFCTR_UFC_SEL",
+ "counter": "RBBM_PERFCTR_UFC",
+ "countable_type": "a8xx_ufc_perfcounter_select"
+ },
+ {
+ "name": "BV_CP",
+ "num": 7,
+ "select_offset": 14,
+ "select": "CP_PERFCTR_CP_SEL",
+ "counter": "RBBM_PERFCTR2_CP",
+ "countable_type": "a8xx_cp_perfcounter_select"
+ },
+ {
+ "name": "BV_PC",
+ "pipe": "BV",
+ "num": 8,
+ "select_offset": 8,
+ "select": "PC_PERFCTR_PC_SEL",
+ "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
+ "counter": "RBBM_PERFCTR_BV_PC",
+ "countable_type": "a8xx_pc_perfcounter_select"
+ },
+ {
+ "name": "BV_VFD",
+ "pipe": "BV",
+ "num": 8,
+ "select_offset": 8,
+ "select": "VFD_PERFCTR_VFD_SEL",
+ "counter": "RBBM_PERFCTR_BV_VFD",
+ "countable_type": "a8xx_vfd_perfcounter_select"
+ },
+ {
+ "name": "BV_VPC",
+ "pipe": "BV",
+ "num": 6,
+ "select_offset": 6,
+ "select": "VPC_PERFCTR_VPC_SEL",
+ "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
+ "counter": "RBBM_PERFCTR_BV_VPC",
+ "countable_type": "a8xx_vpc_perfcounter_select"
+ },
+ {
+ "name": "BV_TP",
+ "pipe": "BV",
+ "num": 8,
+ "select_offset": 12,
+ "select": "TPL1_PERFCTR_TP_SEL",
+ "counter": "RBBM_PERFCTR2_TP",
+ "countable_type": "a8xx_tp_perfcounter_select"
+ },
+ {
+ "name": "BV_SP",
+ "pipe": "BV",
+ "num": 12,
+ "select_offset": 24,
+ "select": "SP_PERFCTR_SP_SEL",
+ "counter": "RBBM_PERFCTR2_SP",
+ "countable_type": "a8xx_sp_perfcounter_select"
+ },
+ {
+ "name": "BV_UFC",
+ "pipe": "BV",
+ "num": 2,
+ "select_offset": 4,
+ "select": "RB_PERFCTR_UFC_SEL",
+ "counter": "RBBM_PERFCTR2_UFC",
+ "countable_type": "a8xx_ufc_perfcounter_select"
+ },
+ {
+ "name": "BV_TSE",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_TSE_SEL",
+ "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
+ "counter": "RBBM_PERFCTR_BV_TSE",
+ "countable_type": "a8xx_tse_perfcounter_select"
+ },
+ {
+ "name": "BV_RAS",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_RAS_SEL",
+ "counter": "RBBM_PERFCTR_BV_RAS",
+ "countable_type": "a8xx_ras_perfcounter_select"
+ },
+ {
+ "name": "BV_LRZ",
+ "pipe": "BV",
+ "num": 4,
+ "select": "GRAS_PERFCTR_LRZ_SEL",
+ "counter": "RBBM_PERFCTR_BV_LRZ",
+ "countable_type": "a8xx_lrz_perfcounter_select"
+ },
+ {
+ "name": "BV_HLSQ",
+ "pipe": "BV",
+ "num": 6,
+ "select": "SP_PERFCTR_HLSQ_SEL",
+ "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
+ "counter": "RBBM_PERFCTR2_HLSQ",
+ "countable_type": "a8xx_hlsq_perfcounter_select"
+ }
+ ]
+}
--
2.53.0