Re: [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC

[Shawn Guo]

On Mon, Apr 20, 2026 at 10:23:20AM +0200, Konrad Dybcio wrote:
> On 4/20/26 5:49 AM, Shawn Guo wrote:
> > This series adds CPUCP mailbox controller support for Qualcomm Nord SoC.
> > 
> > The Nord CPUCP mailbox is functionally identical to the existing x1e80100
> > implementation, except it exposes 16 IPC channels instead of 3.  Patch 1
> > adds the Nord compatible string to the DT binding.  Patch 2 refactors
> > the channel count from a hardcoded compile-time constant into
> > a per-hardware configuration struct populated via the device tree
> > match data.
> 
> What are these channels used for?

Per my search on internal documents, it says that more channels are added
to support following communications:

 - Between Hypervisor software and CPUCP firmware
 - Between TZ software and CPUCP firmware
 - IPC between CPUCPs (Nord chiplet design)

Deepti,

Correct me or add anything as needed.

Shawn