Re: [PATCH 1/4] iommu/amd: Drop unused global exclusion range fields and init

[Yu Zhang]

This patch overlaps with mine [1], which was sent on March 31st with
you on Cc. Jacob has reviewed it.

While I was still waiting on your comments, I realized your series
goes beyond the dead code removal. So I believe I do not need to follow
up on mine.

[1] https://lore.kernel.org/all/20260331152550.479841-1-zhangyu1@xxxxxxxxxxxxxxxxxxx/

Thanks,
Yu


On Mon, Apr 20, 2026 at 05:00:30PM +0000, Suravee Suthikulpanit wrote:
> Remove unused struct amd_iommu.exclusion_start/exclusion_length, the
> MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct
> amd_iommu fields were never assigned, so early_enable_iommu() never
> programmed the hardware exclusion registers through this path.
> 
> Please note that the exclusion range registers have been repurposed
> to SNP completion-wait store base / limit registers. So, rename
> MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead.
> 
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
> ---
>  drivers/iommu/amd/amd_iommu_types.h | 13 ++-----------
>  drivers/iommu/amd/init.c            | 29 +++--------------------------
>  2 files changed, 5 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index c685d3771436..c4ea701b7cab 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -50,17 +50,13 @@
>  #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
>  #define MMIO_MSI_NUM(x)	((x) & 0x1f)
>  
> -/* Flag masks for the AMD IOMMU exclusion range */
> -#define MMIO_EXCL_ENABLE_MASK 0x01ULL
> -#define MMIO_EXCL_ALLOW_MASK  0x02ULL
> -
>  /* Used offsets into the MMIO space */
>  #define MMIO_DEV_TABLE_OFFSET   0x0000
>  #define MMIO_CMD_BUF_OFFSET     0x0008
>  #define MMIO_EVT_BUF_OFFSET     0x0010
>  #define MMIO_CONTROL_OFFSET     0x0018
> -#define MMIO_EXCL_BASE_OFFSET   0x0020
> -#define MMIO_EXCL_LIMIT_OFFSET  0x0028
> +#define MMIO_COMPL_STORE_BASE_OFFSET   0x0020
> +#define MMIO_COMPL_STORE_LIMIT_OFFSET  0x0028
>  #define MMIO_EXT_FEATURES	0x0030
>  #define MMIO_PPR_LOG_OFFSET	0x0038
>  #define MMIO_GA_LOG_BASE_OFFSET	0x00e0
> @@ -680,11 +676,6 @@ struct amd_iommu {
>  	/* pci domain of this IOMMU */
>  	struct amd_iommu_pci_seg *pci_seg;
>  
> -	/* start of exclusion range of that IOMMU */
> -	u64 exclusion_start;
> -	/* length of exclusion range of that IOMMU */
> -	u64 exclusion_length;
> -
>  	/* command buffer virtual address */
>  	u8 *cmd_buf;
>  	u32 cmd_buf_head;
> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
> index f3fd7f39efb4..866249d3673e 100644
> --- a/drivers/iommu/amd/init.c
> +++ b/drivers/iommu/amd/init.c
> @@ -352,28 +352,6 @@ static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
>   *
>   ****************************************************************************/
>  
> -/*
> - * This function set the exclusion range in the IOMMU. DMA accesses to the
> - * exclusion range are passed through untranslated
> - */
> -static void iommu_set_exclusion_range(struct amd_iommu *iommu)
> -{
> -	u64 start = iommu->exclusion_start & PAGE_MASK;
> -	u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
> -	u64 entry;
> -
> -	if (!iommu->exclusion_start)
> -		return;
> -
> -	entry = start | MMIO_EXCL_ENABLE_MASK;
> -	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
> -			&entry, sizeof(entry));
> -
> -	entry = limit;
> -	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
> -			&entry, sizeof(entry));
> -}
> -
>  static void iommu_set_cwwb_range(struct amd_iommu *iommu)
>  {
>  	u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);
> @@ -386,14 +364,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu)
>  	 * Re-purpose Exclusion base/limit registers for Completion wait
>  	 * write-back base/limit.
>  	 */
> -	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
> +	memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET,
>  		    &entry, sizeof(entry));
>  
>  	/* Note:
>  	 * Default to 4 Kbytes, which can be specified by setting base
>  	 * address equal to the limit address.
>  	 */
> -	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
> +	memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET,
>  		    &entry, sizeof(entry));
>  }
>  
> @@ -1013,7 +991,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu)
>  		 * completion wait buffer (CWB) address. Read and re-use it.
>  		 */
>  		pr_info_once("Re-using CWB buffers from the previous kernel\n");
> -		paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK;
> +		paddr = readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_ADDR_MASK;
>  		iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE);
>  		if (!iommu->cmd_sem)
>  			return -ENOMEM;
> @@ -2891,7 +2869,6 @@ static void early_enable_iommu(struct amd_iommu *iommu)
>  	iommu_set_device_table(iommu);
>  	iommu_enable_command_buffer(iommu);
>  	iommu_enable_event_buffer(iommu);
> -	iommu_set_exclusion_range(iommu);
>  	iommu_enable_gt(iommu);
>  	iommu_enable_ga(iommu);
>  	iommu_enable_xt(iommu);
> -- 
> 2.34.1
>