Re: [PATCH v2 2/2] pinctrl: qcom: eliza: Split up some QUP pin groups

[Konrad Dybcio]

On 4/21/26 6:50 PM, Alexander Koskovich wrote:
> On Tuesday, April 21st, 2026 at 9:06 AM, Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:
> 
>> On 4/20/26 4:28 PM, Alexander Koskovich wrote:
>>> Multiple QUPs have lanes that can be routed to one of two GPIOs and
>>> collapsing them prevents devicetrees from requesting specific routing.
>>>
>>> For example, a board that wires an I2C SCL line to one of two GPIOs
>>> cannot request that specific pin with the groups collapsed.
>>>
>>> This change splits them up so devicetrees can request the configuration
>>> they need.
>>
>> Please massage the commit message so that it highlights that the issue
>> is that there are multiple functions defined for a given pin, sharing
>> the same name
> 
> Will do in v3, also I was looking at how sm8550 handles this with qup2_se0, and
> noticed they don't split every lane in this case, they only split out the
> lanes that have two possible GPIOS:
> 
> 	msm_mux_qup2_se0_l0_mira,
> 	msm_mux_qup2_se0_l0_mirb,
> 	msm_mux_qup2_se0_l1_mira,
> 	msm_mux_qup2_se0_l1_mirb,
> 	msm_mux_qup2_se0_l2_mira,
> 	msm_mux_qup2_se0_l2_mirb,
> 	msm_mux_qup2_se0_l3_mira,
> 	msm_mux_qup2_se0_l3_mirb,
> 
> For Eliza I split them all out since I figured if I was already splitting some
> out for mira/mirb I should just also split the rest, but should I mirror this?

I'm a fan of keeping it minimal and only splitting where necessary

Konrad