Re: [PATCH v2 1/5] pinctrl: renesas: rzg2l: Fix SMT register cache handling

[Geert Uytterhoeven]

On Mon, 13 Apr 2026 at 20:25, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Store SMT register cache per bank instead of using a single array.
>
> On RZ/V2H(P), the SMT register is split across two 32-bit registers: bits

Also on RZ/V2N, and RZ/G3E.

> 0/8/16/24 control pins 0-3, while pins 4-7 are controlled by the
> corresponding bits in the next register. The previous implementation
> cached only a single SMT register, leading to incomplete save/restore of
> SMT state.
>
> Convert cache->smt to a per-bank array and allocate storage for both
> halves. Update suspend/resume handling to save and restore both SMT
> registers when present.
>
> Fixes: 837afa592c623 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl-fixes for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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when I'm talking to journalists I just say "programmer" or something like that.
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