[PATCH v2 8/8] fs/resctrl: Add the documentation for Global Slow Memory Bandwidth Allocation

[Babu Moger]

AMD Global Slow Memory Bandwidth Allocation (GSMBA) is the slow-memory
(CXL.memory) counterpart of GMBA. Like GMBA it applies bandwidth limits to
groups of threads that span multiple QoS (L3) domains, using the same GMBA
control domains that are aligned to the system's NPS (Nodes Per Socket)
configuration. GSMBA is exposed in the schemata file under the resource
label "GSMBA", with values in multiples of 1 GB/s.

Document GSMBA in Documentation/filesystems/resctrl.rst:

- Add GSMBA to the resctrl feature table at the top of the file.
- Add a "Global Slow Memory Bandwidth Allocation (GSMBA)" section
  describing the resource, its bandwidth domain and the schemata syntax and
  unit.
- Add a "Reading/writing the schemata file (on AMD systems) with GSMBA
  feature" section with a worked example.

Signed-off-by: Babu Moger <babu.moger@xxxxxxx>
---
v2: Updated the documentation with clarity and format issues.
    Improved changelog.
---
 Documentation/filesystems/resctrl.rst | 42 +++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesystems/resctrl.rst
index 901d059800fa..a1c5aa45f5fe 100644
--- a/Documentation/filesystems/resctrl.rst
+++ b/Documentation/filesystems/resctrl.rst
@@ -29,6 +29,7 @@ BMEC (Bandwidth Monitoring Event Configuration)			""
 ABMC (Assignable Bandwidth Monitoring Counters)			""
 SDCIAE (Smart Data Cache Injection Allocation Enforcement)	""
 GMBA (Global Memory Bandwidth Allocation)			""
+GSMBA (Global Slow Memory Bandwidth Allocation)			""
 =============================================================== ================================
 
 Historically, new features were made visible by default in /proc/cpuinfo. This
@@ -1001,6 +1002,22 @@ is formatted as:
 
 	SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
 
+Global Slow Memory Bandwidth Allocation (GSMBA)
+-----------------------------------------------
+
+AMD hardware supports Global Slow Memory Bandwidth Allocation (GSMBA).
+GSMBA provides a mechanism for software to specify slow-memory bandwidth
+limits for groups of threads that span multiple QoS (L3) domains. Each
+such collection of QoS domains is called a GSMBA control domain. GSMBA
+operates similarly to GMBA, but targets slow memory (CXL.memory) instead
+of DRAM; it reuses the same NPS-aligned control domains as GMBA.
+
+The bandwidth domain for GSMBA is the GSMBA control domain. GSMBA is
+exposed in the schemata file under the resource label ``GSMBA``, with
+values expressed in multiples of 1 GB/s::
+
+	GSMBA:<domain_id0>=bw_GBps0;<domain_id1>=bw_GBps1;...
+
 Reading/writing the schemata file
 ---------------------------------
 Reading the schemata file will show the state of all resources
@@ -1077,6 +1094,31 @@ For example, to allocate 8GB/s limit on the first cache id:
       MB:0=2048;1=2048;2=2048;3=2048
       L3:0=ffff;1=ffff;2=ffff;3=ffff
 
+Reading/writing the schemata file (on AMD systems) with GSMBA feature
+---------------------------------------------------------------------
+Reading the schemata file shows the current bandwidth limit on every
+GSMBA control domain. Values are in multiples of 1 GB/s.
+
+For example, to set an 8 GB/s limit on GSMBA control domain 0, leaving
+control domain 1 at its previous limit:
+
+::
+
+  # cat schemata
+    GSMBA:0=4096;1=4096
+     SMBA:0=8192;1=8192;2=8192;3=8192
+      GMB:0=4096;1=4096
+       MB:0=8192;1=8192;2=8192;3=8192
+       L3:0=ffff;1=ffff;2=ffff;3=ffff
+
+  # echo "GSMBA:0=8" > schemata
+  # cat schemata
+    GSMBA:0=   8;1=4096
+     SMBA:0=8192;1=8192;2=8192;3=8192
+      GMB:0=4096;1=4096
+       MB:0=8192;1=8192;2=8192;3=8192
+       L3:0=ffff;1=ffff;2=ffff;3=ffff
+
 Cache Pseudo-Locking
 ====================
 CAT enables a user to specify the amount of cache space that an
-- 
2.43.0