[PATCH 0/3] PCI: altera: Add Agilex 5 PCIe Root Port support

[Mahesh Vaidya]

This series adds PCIe Root Port controller support for the Intel
Agilex 5 family of SoC FPGAs to the existing pcie-altera driver.

The Agilex 5 PCIe Hard IP reuses the same config-space access path
as Agilex 7 (V3). Root port and endpoint configuration reads/writes
use direct MMIO to the HIP and CRA regions.

The difference is in the HIP port-level registers (IRQ status and IRQ
enable). On V3 these are directly mapped through the Hip MMIO window.
On V4 these registers are only reachable through an indirect access
mailbox (CFG REG IA CTRL) in the PCIe Subsystem AXI-Lite interface,
documented in the GTS AXI Streaming IP for PCIe User Guide.

The indirect access sequence writes the target address and control
bits to the mailbox registers, polls for completion, then reads the
result. Since the chained IRQ handler runs in hardirq context,
readl_poll_timeout_atomic is used with a 1ms timeout.

Tested on an Agilex 5 E-series Premium Development Kit with an
NVMe endpoint. Verified:
  - PCIe link-up at the expected width and speed
  - NVMe endpoint enumeration and binding to the nvme driver
  - NVMe read/write I/O via fio with no errors or timeouts
  - MSI interrupt delivery observed via /proc/interrupts during I/O

Patch 1 adds the DT binding compatible string for Agilex 5.
Patch 2 fixes pre-existing resource leaks in the probe error path,
        which the Agilex 5 support patch depends on.
Patch 3 adds the V4 driver support: indirect register access helpers,
        the chained IRQ handler, and the platform data.

Mahesh Vaidya (3):
  dt-bindings: PCI: altera: add binding for Agilex 5
  PCI: altera: fix resource leaks on probe failure
  PCI: altera: add Agilex 5 support

 .../bindings/pci/altr,pcie-root-port.yaml     |  37 ++--
 drivers/pci/controller/pcie-altera.c          | 173 +++++++++++++++++-
 2 files changed, 190 insertions(+), 20 deletions(-)


base-commit: 4224e91fea5695a89843b4c38283016616946307
-- 
2.34.1