[PATCH v5 0/2] arm64: dts: qcom: add IMEM and PIL regions for glymur

[Ananthu C V]

This series adds dt binding and node for IMEM on glymur.

changes in v5:
- updated reg size to cover the whole imem region instead of only the shared imem
- picked up reviewd-by for the dt node
- Link to v4: https://lore.kernel.org/all/20260327-glymur-imem-v4-0-8fe0f20ad9fd@xxxxxxxxxxxxxxxx/

changes in v4:
- picked up acked-by for the dt-binding
- added dt node for imem on glymur
- rebased the commits
- link to v3: https://lore.kernel.org/all/20260129071435.2624252-1-ananthu.cv@xxxxxxxxxxxxxxxx/

changes in v3:
- moved dt-binding to sram.yaml for mmio-sram fallback
- link to v2: https://lore.kernel.org/all/20260123101501.2836551-2-ananthu.cv@xxxxxxxxxxxxxxxx/

changes in v2:
- alphabetically sorted the placement of glymur in the list
- link to v1: https://lore.kernel.org/all/20260122093319.2124906-1-ananthu.cv@xxxxxxxxxxxxxxxx/

Signed-off-by: Ananthu C V <ananthu.cv@xxxxxxxxxxxxxxxx>
---
Ananthu C V (2):
      dt-bindings: sram: document glymur as compatible
      arch: arm64: boot: dts: qcom: add IMEM and PIL regions for glymur

 Documentation/devicetree/bindings/sram/sram.yaml |  1 +
 arch/arm64/boot/dts/qcom/glymur.dtsi             | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
---
base-commit: 4c406406070d57dbefeaad149181785330c23f92
change-id: 20260424-glymur-imem-970c1015e89b

Best regards,
--  
Ananthu C V <ananthu.cv@xxxxxxxxxxxxxxxx>