Re: [PATCH 1/3] dt-bindings: PCI: altera: add binding for Agilex 5

[Krzysztof Kozlowski]

On Fri, Apr 24, 2026 at 02:49:11AM -0700, Mahesh Vaidya wrote:
>      enum:
>        - altr,pcie-root-port-1.0
> @@ -25,20 +26,15 @@ properties:
>        - altr,pcie-root-port-3.0-f-tile
>        - altr,pcie-root-port-3.0-p-tile
>        - altr,pcie-root-port-3.0-r-tile
> +      - altr,pcie-root-port-4.0
>  
>    reg:
> -    items:
> -      - description: TX slave port region
> -      - description: Control register access region
> -      - description: Hard IP region

I don't understand why you are removing this.

>      minItems: 2
> +    maxItems: 3
>  
>    reg-names:
> -    items:
> -      - const: Txs
> -      - const: Cra
> -      - const: Hip
>      minItems: 2
> +    maxItems: 3
>  
>    interrupts:
>      maxItems: 1
> @@ -80,18 +76,25 @@ allOf:
>      then:
>        properties:
>          reg:
> -          maxItems: 2
> -
> +          items:
> +            - description: TX slave port region
> +            - description: Control register access region
>          reg-names:
> -          maxItems: 2
> -
> +          items:
> +            - const: Txs
> +            - const: Cra
>      else:
>        properties:
>          reg:
> -          minItems: 3
> -
> +          items:
> +            - description: TX slave port region
> +            - description: Control register access region
> +            - description: Hard IP region
>          reg-names:
> -          minItems: 3
> +          items:
> +            - const: Txs
> +            - const: Cra
> +            - const: Hip

So it's the same... Confusing or I miss here something.

Best regards,
Krzysztof