Re: [PATCH 2/5] clk: renesas: r9a08g046: Add CA55 core clocks

From: Geert Uytterhoeven

Date: Mon Apr 27 2026 - 05:35:53 EST


On Fri, 24 Apr 2026 at 15:24, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> > On Mon, 30 Mar 2026 at 15:23, Biju <biju.das.au@xxxxxxxxx> wrote:
> > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > >
> > > Add CA55 core clock entries.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > > --- a/drivers/clk/renesas/r9a08g046-cpg.c
> > > +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> >
> > > @@ -25,15 +26,24 @@
> > > #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
> > > #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
> > > #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
> > > +#define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3)
> > > +#define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3)
> > > +#define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3)
> > > +#define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3)
> > > #define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2)
> > > #define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
> > > #define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
> > > #define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1)
> > >
> > > /* RZ/G3L Clock status configuration. */
> > > +#define G3L_DIVPL1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 0, 1)
> >
> > G3L_DIVPL1_STS is unused. Perhaps you wanted to add the I-clock, too?
> > If not, please let me know, and I can drop this while applying.
>
> Please drop it.

OK.

> > The rest LGTM, so
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Thanks, will queue in renesas-clk for v7.2.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds