[PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node

[William Bright]

Add the SDC4 SDHCI controller node for the SM8550 SoC.

SMMU stream ID 0x80 was sourced from the UEFI bootloader IORT tables,
as SDCC stream IDs are not documented in the register reference manual.
Unlike SDC2, the data path is routed via aggre1_noc, matching
MASTER_SDCC_4 in drivers/interconnect/qcom/sm8550.c.

The SDHCI capabilities register on this SoC advertises SDR104
and SDR50 but these UHS-I modes are broken on SDHC4.
Mask them via sdhci-caps-mask, this keeps the bus in HS mode,
which initialises reliably.

Tested on the IMDT QCS8550 SBC. This board is not currently
supported in-tree.

Co-developed-by: Tendai Makumire <tendai.makumire@xxxxxxxxxxx>
Signed-off-by: Tendai Makumire <tendai.makumire@xxxxxxxxxxx>
Signed-off-by: William Bright <william.bright@xxxxxxxxxxx>
---
Changes in v2:
- Drop qcom,dll-config and qcom,ddr-config; these properties are not
  valid for this SDC instance (Konrad Dybcio)
- Reduce the OPP table to a single 75 MHz / low_svs entry matching the
  SDCC4 operating point on this SoC (Konrad Dybcio)
- Forbid SDR104/SDR50 via sdhci-caps-mask, matching the previously
  existing sdhc_2 workaround in the same file.
  The SDHCI capabilities register on this SoC advertises SDR50/SDR104
  modes that are broken on sdhc_4; without masking them the MMC
  core selects SDR50 and fails DLL tuning with
  -ETIMEDOUT during SDIO card initialisation.
- Rework the commit message to reflect the above understanding and
  drop the "root cause not yet determined" note
- Drop self Tested-by tag (Konrad Dybcio)
- Link to v1: https://patch.msgid.link/20260423-sm8550-sdhc4-support-v1-1-93fd81fea5d9@xxxxxxxxxxx

To: Bjorn Andersson <andersson@xxxxxxxxxx>
To: Konrad Dybcio <konradybcio@xxxxxxxxxx>
To: Rob Herring <robh@xxxxxxxxxx>
To: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
To: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: linux-arm-msm@xxxxxxxxxxxxxxx
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6..07161a873b2d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3280,6 +3280,46 @@ opp-202000000 {
 			};
 		};
 
+		sdhc_4: mmc@8844000 {
+			compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08844000 0 0x1000>;
+
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC4_AHB_CLK>,
+				 <&gcc GCC_SDCC4_APPS_CLK>,
+				 <&bi_tcxo_div2>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0x80 0>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc4_opp_table>;
+
+			interconnects = <&aggre1_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+			bus-width = <4>;
+			max-sd-hs-hz = <37500000>;
+			dma-coherent;
+
+			/* Forbid SDR104/SDR50 broken hw! */
+			sdhci-caps-mask = <0x3 0>;
+
+			status = "disabled";
+
+			sdhc4_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-75000000 {
+					opp-hz = /bits/ 64 <75000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+			};
+		};
+
 		iris: video-codec@aa00000 {
 			compatible = "qcom,sm8550-iris";
 

---
base-commit: 4f5b4b748ac75683d61c304ee3ee0db235e8f312
change-id: 20260423-sm8550-sdhc4-support-358bf264c04e

Best regards,
--  
William Bright <william.bright@xxxxxxxxxxx>