[PATCH v4 0/7] Add Renesas RZ/G3L PINCONTROL support

[Biju]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Hi All,

This patch series aims to add basic pin-control support for the Renesas
RZ/G3L SoC. The RZ/G3L pinctrl has an OTHER_POC register compared to other
SoCs for setting the IO domain voltage for AWO, ISO, and WDT.

Document the bindings for the RZ/G3L SoC and add pinctrl definitions in
the driver. Some IPs need to set the register IPCONT_SEL_CLONECH in SYSC
to control the clone channel of the IP.

v3->v4:
 * Dropped patch#1 and #3 from the series as it is accepted.
 * Dropped Port P4 from binding header as it does not exist on RZ/G3L SoC.
 * Retained the tag for bindings as it is trivial change.
 * Added a patch to make QSPI register handling conditional.
 * Updated commit description for patch#3.
 * Updated rzg2l_caps_to_pwr_reg() to return mask in addition to register
   offset.
 * Dropped ffs(), using field_get() instead to get PoC offset in
   rzg2l_get_power_source().
 * Simplified rzg2l_set_power_source() by using mask from
   rzg2l_caps_to_pwr_reg().
 * Added scoped_guard() for RMW operation in rzg2l_set_power_source().
 * Added a patch to update rzg2l_pin_to_oen_bit() so that it can reuse on
   RZ/G3L.
 * Dropped extra white spaces in SD0_CLK and SD0_DATA0 entries.
 * Renamed SD0_DATA* → SD0_DAT* to match the pin function spreadsheet.
 * Renamed SCIF_{RXD,TXD} → SCIF0_{RXD,TXD} to match the pin function
   spreadsheet.
 * .pin_to_oen_bit = rzg2l_pin_to_oen_bit() and dropped oen_max_port from
   rzg3l_hwcfg.
 * Updated the data type of func varaible from u8 to unsigned int.
 * Collected the tag.
 * Started using an 8-bit pin mask instead of start and end pin indices,
   and combined multiple entries with the same port number and config
   using ORed values of BIT() and GENMASK(), thereby reducing table size.
 * Started using an 8-bit function mask instead of a function index, and
   got rid of the shared pin bit. This also provides info about the
   possible functions.
 * Dropped RZG3L_CLONE_CHANNEL_{PACK,DTAT,SHARED_PIN_MASK} macros.
 * Replaced RZG3L_CLONE_CHANNEL_CFG_PIN_{START,END}_MASK macro with
   RZG3L_CLONE_CHANNEL_PIN_MASK.
 * Replaced RZG3L_CLONE_CHANNEL_CFG_PORT_MASK macro with
   RZG3L_CLONE_CHANNEL_PORT_MASK.
 * Updated kernel doc comment for clone register from 'registers' to
   'register'.
 * Dropped dynamic allocation for the clone register cache, instead using
   static allocation in struct rzg2l_pinctrl_reg_cache, as it is a single
   32-bit register.
 * Replaced the LUT and for loop in rzg2l_pinctrl_set_clone_mode() with a
   simple switch statement.
 * Dropped the complex check to find the func match in
   rzg2l_pinctrl_set_clone_mode() by using pin_func_mask & BIT(func).
 * Dropped the inner for loop for finding a pin match in
   rzg2l_pinctrl_set_clone_mode() by using pin_mask & BIT(pin).
 * Dropped field_prep with "val << bit" in rzg2l_pinctrl_set_clone_mode()
   as val is just 0 or 1.
 * In rzg2l_pinctrl_probe(), replaced the temporary variable offset with
   &pctrl->clone_offset.
 * Replaced RZG3L_CLONE_CHANNEL_PIN_CFG_PACK with RZG3L_CLONE_CHANNEL_DATA,
   and replaced clone_pin_configs, n_clone_pins,
   r9a08g046_clone_channel_pin_cfg with clone_channel_data,
   n_clone_channel_data, and r9a08g046_clone_channel_data.
v2->v3:
 * Dropped clk, pincontrol device node and pincontrol support for SCIF0
   and GBETH nodes from this series. Will add this later.
 * Documented renesas,clonech property for controlling clone channel
   control register located on SYSC IP block on RZ/G3L SoC.
 * Retained the tag as it is similar change for RZ/G3E thermal bindings.
 * Updated r9a08g046_gpio_configs[] by replacing the typo AWO->ISO.
 * Added PIN_CFG_PUPD to RZG3L_MPXED_ETH_PIN_FUNCS macro
 * Replaced RZG2L_MPXED_COMMON_PIN_FUNCS->RZG3L_MPXED_PIN_FUNCS in 
   RZG3L_MPXED_PIN_FUNCS_POC macro for setting power source for pins.
 * Added clone channel control support in the driver
v1->v2:
 * Split DTSI patches from bindings
 * Fix typo maxItems->minItems in bindings
 * Collected the tag

Biju Das (7):
  dt-bindings: pinctrl: renesas: Document RZ/G3L SoC
  pinctrl: renesas: rzg2l: Make QSPI register handling conditional
  pinctrl: renesas: rzg2l: Add support for selecting power source for
    {WDT,AWO,ISO}
  pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match
  pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC
  pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()
  pinctrl: renesas: rzg2l: Add support for clone channel control

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  20 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 485 +++++++++++++++++-
 .../pinctrl/renesas,r9a08g046-pinctrl.h       |  38 ++
 3 files changed, 526 insertions(+), 17 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h

-- 
2.43.0