Re: [PATCH v2] i3c: dw-i3c-master: Fix IBI count register selection for versalnet

[Alexandre Belloni]

On Wed, 01 Apr 2026 14:14:30 +0530, Shubhrajyoti Datta wrote:
> On DesignWare I3C controllers where IC_HAS_IBI_DATA=0 (such as versalnet),
> the IBI_STS_CNT field (bits [28:24] of QUEUE_STATUS_LEVEL) is hardwired
> to 0. The IBI status entry count is instead reported via IBI_BUF_BLR
> (bits [23:16] of the same register).
> 
> irq_handle_ibis() was unconditionally reading IBI_STS_CNT, causing it to
> always see 0 pending IBIs on versalnet and return early without draining
> the IBI buffer. Since INTR_IBI_THLD_STAT is level-triggered against the
> buffer fill level, this left the interrupt permanently asserted.
> 
> [...]

Applied, thanks!

[1/1] i3c: dw-i3c-master: Fix IBI count register selection for versalnet
      https://git.kernel.org/i3c/c/1d78a8fc97c1

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com