Re: [PATCH v12 07/22] gpu: nova-core: mm: Add TLB flush support

[Alexandre Courbot]

On Sun Apr 26, 2026 at 6:14 AM JST, Joel Fernandes wrote:
<snip>
> +    /// TLB flush control register.
> +    pub(crate) NV_TLB_FLUSH_CTRL(u32) @ 0x00b830b0 {
> +        /// Invalidate every VA in the PDB selected by `NV_TLB_FLUSH_PDB_LO/HI`.
> +        0:0     all_va => bool;
> +        /// Invalidate TLBs for all PDBs (ignores `NV_TLB_FLUSH_PDB_LO/HI`).
> +        1:1     all_pdb => bool;
> +        /// Restrict the flush to the HUB MMU's TLBs; skip broadcasting to the
> +        /// per-GPC L2 TLBs.
> +        ///
> +        /// The GPU MMU has a two-level TLB hierarchy:
> +        /// 1. The *HUB MMU* sits at the top and serves memory requests from
> +        ///    "host-side" engines: the host/channel interface, copy engines,
> +        ///    display, and BAR1/BAR2 accesses.
> +        /// 2. Each GPC (Graphics Processing Cluster — the block that houses
> +        ///    shader cores / SMs) has its own L2 TLB that serves requests from
> +        ///    the compute and graphics engines inside the cluster.
> +        ///
> +        /// When set, only the HUB TLBs are invalidated. This is a performance
> +        /// optimization for flushes that only affect HUB-side mappings (e.g.
> +        /// BAR1/BAR2 windows), where fanning the invalidation out to every
> +        /// GPC's L2 TLB would be wasted work. Must be false when flushing
> +        /// mappings that may be cached by compute/graphics engines.
> +        2:2     hubtlb_only => bool;
> +        /// Invalidation acknowledgment scope. See [`TlbAckMode`] for details.
> +        8:7     ack ?=> TlbAckMode;
> +        /// Write 1 to kick off the flush. Hardware clears this bit when the
> +        /// flush completes; reads as 1 while the flush is in progress.
> +        31:31   trigger => bool;
> +    }
> +}

Registers should be defined with their upper fields first (i.e. `31:31`
on top).