Re: [PATCH v12 09/22] gpu: nova-core: mm: Add common types for all page table formats

[Joel Fernandes]

On 5/2/2026 11:42 AM, Alexandre Courbot wrote:
> On Sun Apr 26, 2026 at 6:14 AM JST, Joel Fernandes wrote:
>> Add common page table types shared between MMU v2 and v3. These types
>> are hardware-agnostic and used by both MMU versions.
>>
>> Cc: Nikola Djukic <ndjukic@xxxxxxxxxx>
>> Signed-off-by: Joel Fernandes <joelagnelf@xxxxxxxxxx>
>> ---
>>  drivers/gpu/nova-core/mm.rs           |   1 +
>>  drivers/gpu/nova-core/mm/pagetable.rs | 157 ++++++++++++++++++++++++++
>>  2 files changed, 158 insertions(+)
>>  create mode 100644 drivers/gpu/nova-core/mm/pagetable.rs
>>
>> diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs
>> index 8b8a86980bb6..045e35c92b78 100644
>> --- a/drivers/gpu/nova-core/mm.rs
>> +++ b/drivers/gpu/nova-core/mm.rs
>> @@ -32,6 +32,7 @@ macro_rules! impl_pfn_bounded {
>>      };
>>  }
>>  
>> +pub(super) mod pagetable;
>>  pub(crate) mod pramin;
>>  pub(super) mod tlb;
>>  
>> diff --git a/drivers/gpu/nova-core/mm/pagetable.rs b/drivers/gpu/nova-core/mm/pagetable.rs
>> new file mode 100644
>> index 000000000000..637ff43ea83a
>> --- /dev/null
>> +++ b/drivers/gpu/nova-core/mm/pagetable.rs
>> @@ -0,0 +1,157 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +//! Common page table types shared between MMU v2 and v3.
>> +//!
>> +//! This module provides foundational types used by both MMU versions:
>> +//! - Page table level hierarchy
>> +//! - Memory aperture types for PDEs and PTEs
>> +
>> +#![expect(dead_code)]
>> +
>> +use kernel::num::Bounded;
>> +
>> +use crate::gpu::Architecture;
>> +
>> +/// Extracts the page table index at a given level from a virtual address.
>> +pub(super) trait VaLevelIndex {
>> +    /// Return the page table index at `level` for this virtual address.
>> +    fn level_index(&self, level: u64) -> u64;
>> +}
>> +
>> +/// MMU version enumeration.
>> +#[derive(Debug, Clone, Copy, PartialEq, Eq)]
>> +pub(crate) enum MmuVersion {
>> +    /// MMU v2 for Turing/Ampere/Ada.
>> +    V2,
>> +    /// MMU v3 for Hopper and later.
>> +    V3,
>> +}
>> +
>> +impl From<Architecture> for MmuVersion {
>> +    fn from(arch: Architecture) -> Self {
>> +        match arch {
>> +            Architecture::Turing | Architecture::Ampere | Architecture::Ada => Self::V2,
>> +            // In the future, uncomment the following to support V3.
>> +            // _ => Self::V3,
> 
> The architecture definitions for Blackwell are now in `drm-rust-next`,
> so I think the next iteration can handle this.
> 
> Which reminds me: is V3 working? I remember some fixup by Eliot
> wandering around, have you integrated it to the series?

MMU v3 is working. But this series needs more patches on top of it for
Blackwell, I am carrying those extras in a different tree based on this
series. The fixes from have all been integrated (either in this series or
that other tree of extras).

Have all the base blackwell patches made it into drm-rust-next? If yes, I
can rebase this series on it, pull in the extras, and continue posting the
next mm iteration with blackwell support.

Thanks.