Re: [PATCH 7/7] arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist
From: Marek Vasut
Date: Sat May 02 2026 - 22:51:11 EST
On 4/29/26 3:59 PM, Geert Uytterhoeven wrote:
Hello Geert,
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
This include is not needed?
It is not.
+#include "salvator-panel-aa104xd12.dtso"
+
+&{/panel} {
+ data-mapping = "jeida-24";
Is there any specific reason Geist needs "jeida-24", while all other
boards use "jeida-18"?
This is a leftover, it should be jeida-18 , the Geist board pulls LVDS output(LVDS0) pin 19 MODE=L , which on the aa104xd12 means 6-bit mode.
It looks like the major difference between Salvator-X(S) and Geist vs.
Draak and Ebisu is that the former connect to lvds0, and the latter to lvds1.
So what about renaming
salvator-panel-aa104xd12.dtso to lvds0-panel-aa104xd12.dtso, and
draak-ebisu-panel-aa104xd12.dtso to lvds1-panel-aa104xd12.dtso?
Will do in V2, although in a slightly different way.
[...]
+ x22_clk: x22-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33000000>;
+ };
X22 is not wired to anything; should we keep it?
DT is supposed to be hardware description, the xtal is there and the resistor footprint to connect it to the SoC is on the PCB, so someone might populate it and use the xtal. This isn't a particularly convincing argument for keeping the x22 node though.
[...]
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ tx-internal-delay-ps = <2000>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622";
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100>;
+ reset-deassert-us = <100>;
Do we need these two? We don't have them in e.g.
arch/arm64/boot/dts/renesas/salvator-common.dtsi
I believe we should add them, the KSZ9031 PHY does require 100us delay after reset is deasserted and before MDIO access is possible:
https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf
FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING
"
Note 2: After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO)
interface
"
[...]
+ pwm2_pins: pwm2 {
+ groups = "pwm2_a";
+ function = "pwm2";
+ };
What is pwm2 used for?
The signal is accessible on the EXIO connector D (LBSC) .
It is up to user to use the pin for their purposes.
[...]
The rest is addressed, thanks !