Re: [PATCH net-next 14/15] ice: dpll: fix rclk pin state get and misplaced header macros
From: Ivan Vecera
Date: Tue May 05 2026 - 04:36:33 EST
On 5/5/26 12:39 AM, Jacob Keller wrote:
On 4/30/2026 11:37 PM, Jacob Keller wrote:No objections at all! :-)... Please go ahead, rebase and submit.
From: Ivan Vecera <ivecera@xxxxxxxxxx>Ivan,
Fix two issues introduced in commit ad1df4f2d591 ("ice: dpll: Support
E825-C SyncE and dynamic pin discovery"):
* The refactoring of ice_dpll_rclk_state_on_pin_get() to use
ice_dpll_pin_get_parent_idx() omitted the base_rclk_idx adjustment
that was correctly added in the ice_dpll_rclk_state_on_pin_set() path.
This breaks E810 devices where base_rclk_idx is non-zero, causing
the wrong hardware index to be used for pin state lookup and incorrect
recovered clock state to be reported via the DPLL subsystem. E825C is
unaffected as its base_rclk_idx is 0.
* Add bounds check against ICE_DPLL_RCLK_NUM_MAX on hw_idx after the
base_rclk_idx subtraction in both ice_dpll_rclk_state_on_pin_{get,set}()
to prevent out-of-bounds access on the pin state array.
* The CGU register definitions (ICE_CGU_R10, ICE_CGU_R11 and related field
masks) were placed after the #endif of the _ICE_DPLL_H_ include guard,
leaving them unprotected. Move them inside the guard.
Fixes: ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and dynamic pin discovery")
Signed-off-by: Ivan Vecera <ivecera@xxxxxxxxxx>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@xxxxxxxxx>
Signed-off-by: Jacob Keller <jacob.e.keller@xxxxxxxxx>
---
Unless you have any objections I will go ahead and rebase this ontop of
net and submit it in my next round of fixes. I might split the changes
to have the CGU register definitions change in a separate patch since it
conceptually isn't the same issue as the other two.
Thank you.
Ivan