[PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

From: Prabhakar

Date: Tue May 05 2026 - 08:07:05 EST


From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Add xSPI (Expanded SPI) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
The RZ/T2H integrates two xSPI interfaces.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 3761551c9647..a5b570ae82c0 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1006,6 +1006,44 @@ mii_conv3: mii-conv@3 {
};
};

+ xspi0: spi@801c0000 {
+ compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+ reg = <0 0x801c0000 0 0x1000>,
+ <0 0x40000000 0 0x10000000>;
+ reg-names = "regs", "dirmap";
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pulse", "err_pulse";
+ clocks = <&cpg CPG_MOD 4>,
+ <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
+ clock-names = "ahb", "spi";
+ resets = <&cpg 0x4>;
+ reset-names = "hresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ xspi1: spi@801c1000 {
+ compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+ reg = <0 0x801c1000 0 0x1000>,
+ <0 0x50000000 0 0x10000000>;
+ reg-names = "regs", "dirmap";
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pulse", "err_pulse";
+ clocks = <&cpg CPG_MOD 5>,
+ <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
+ clock-names = "ahb", "spi";
+ resets = <&cpg 5>;
+ reset-names = "hresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
reg = <0 0x80280000 0 0x10000>,
--
2.54.0