[PATCH 1/2] arm64: dts: renesas: r9a08g046: Add wdt device node
From: Biju
Date: Tue May 05 2026 - 09:00:05 EST
From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The RZ/G3L SOC has 3 watchdog timer channels:
wdt channel0(wdt0) for Cortex-A55-CPU Non-Secure
wdt channel1(wdt1) for Cortex-A55 CPU Secure
wdt channel2(wdt2) for Cortex-M33 CPU
Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 55cbae6ca8d4..930873ae7786 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -875,6 +875,20 @@ gic: interrupt-controller@12400000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ wdt0: watchdog@12800800 {
+ compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt";
+ reg = <0 0x12800800 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A08G046_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "wdt", "perrout";
+ resets = <&cpg R9A08G046_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
stmmac_axi_setup: stmmac-axi-config {
--
2.43.0