Re: [PATCH v4 2/7] pinctrl: renesas: rzg2l: Make QSPI register handling conditional

[Geert Uytterhoeven]

On Thu, 30 Apr 2026 at 11:34, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> The QSPI register at offset 0x3008 is not present on all SoCs supported by
> the RZ/G2L pinctrl driver. Unconditionally reading and writing this
> register during suspend/resume on hardware that lacks it can cause
> undefined behaviour.
>
> Add a qspi field to rzg2l_register_offsets to allow per-SoC declaration of
> the QSPI register offset, and guard the suspend/resume accesses with a
> check on that field. Populate the offset only for the RZ/{G2L,G2LC,G2UL,
> Five} hardware configuration, which is where the register is known to
> exist.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl for v7.2.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds