RE: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training

[Biju Das]

Hi Hans,

> -----Original Message-----
> From: Hans Zhang <18255117159@xxxxxxx>
> Sent: 06 May 2026 17:21
> Subject: Re: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link
> training
> 
> 
> 
> On 5/6/26 23:31, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: linux-arm-kernel <linux-arm-kernel-bounces@xxxxxxxxxxxxxxxxxxx>
> >> On Behalf Of Hans Zhang
> >> Sent: 06 May 2026 16:24
> >> Subject: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field
> >> and 100 ms delay after link training
> >>
> >> The Cadence LGA (Legacy Architecture IP) PCIe host controller
> >> currently lacks the mandatory 100 ms delay after link training
> >> completes for speeds
> >>> 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1.
> >>
> >> Add a 'max_link_speed' field to struct cdns_pcie to record the
> >> maximum supported link speed (or the currently configured speed). In
> >> the common host layer function cdns_pcie_host_start_link(), after the
> >> link has been successfully established, call pcie_wait_after_link_train() to insert the required
> delay if max_link_speed > 2.
> >>
> >> Glue drivers must set max_link_speed appropriately (e.g., from the
> >> device tree property "max-link-
> >> speed") to enable the delay.
> >>
> >> Signed-off-by: Hans Zhang <18255117159@xxxxxxx>
> >> ---
> >>   drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++
> >>   drivers/pci/controller/cadence/pcie-cadence.h             | 2 ++
> >>   2 files changed, 6 insertions(+)
> >>
> >> diff --git
> >> a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> >> b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> >> index 2b0211870f02..51376f69d007 100644
> >> --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> >> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> >> @@ -14,6 +14,7 @@
> >>
> >>   #include "pcie-cadence.h"
> >>   #include "pcie-cadence-host-common.h"
> >> +#include "../../pci.h"
> >>
> >>   #define LINK_RETRAIN_TIMEOUT HZ
> >>
> >> @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc,
> >>   	if (!ret && rc->quirk_retrain_flag)
> >>   		ret = cdns_pcie_retrain(pcie, pcie_link_up);
> >>
> >> +	if (!ret)
> >> +		pcie_wait_after_link_train(pcie->max_link_speed);
> >> +
> >>   	return ret;
> >>   }
> >>   EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link);
> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h
> >> b/drivers/pci/controller/cadence/pcie-
> >> cadence.h
> >> index 574e9cf4d003..e222b095d2b6 100644
> >> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> >> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> >> @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data {
> >>    * @ops: Platform-specific ops to control various inputs from Cadence PCIe
> >>    *       wrapper
> >>    * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
> >> + * @max_link_speed: maximum supported link speed
> >
> > Maximum to make consistent with other comments?
> 
> Hi Biju,
> 
> The reference I used is:
> 
> drivers/pci/controller/pcie-rzg3s-host.c

* @ops: Platform-specific ops to control various inputs from Cadence PCIe
*       wrapper
* @cdns_pcie_reg_offsets: Register bank offsets for different SoC

Bute here drivers/pci/controller/cadence/pcie-cadence.h, all start with Capital letter.


> 
> drivers/pci/controller/pcie-rzg3s-host.c
> /**
>   ......
>   * @max_link_speed: maximum supported link speed
>   */
> struct rzg3s_pcie_host {
> ......
> 
> 
> >
> >
> >>    */
> >>   struct cdns_pcie {
> >>   	void __iomem		             *reg_base;
> >> @@ -98,6 +99,7 @@ struct cdns_pcie {
> >>   	struct device_link	             **link;
> >>   	const  struct cdns_pcie_ops          *ops;
> >>   	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
> >> +	int				     max_link_speed;
> >
> > unsigned int as speed cannot be negative??
> 
> The following file referred to:
> 
> drivers/pci/controller/dwc/pcie-designware.h
> struct dw_pcie {
>      ......
>      int			max_link_speed;

Maybe that driver is using negative values.
Is this driver using negative values for speed?

Cheers,
Biju

>      ......
> };
> 
> 
> Best regards,
> Hans
> >
> > Cheers,
> > Biju
> >
> >>   };
> >>
> >>   /**
> >> --
> >> 2.34.1
> >>