[PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask
From: Dmitry Baryshkov
Date: Thu May 07 2026 - 02:47:14 EST
From: Dikshita Agarwal <dikshita.agarwal@xxxxxxxxxxxxxxxx>
For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs
from the currently supported VPUs. In preparation for adding AR50LT
support in subsequent patches, introduce a platform data field,
wd_intr_mask, to capture the watchdog interrupt bitmask per platform.
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@xxxxxxxxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/iris/iris_platform_common.h | 1 +
drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++
drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 6 ++++++
drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++---
drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 -
5 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 7acb073f7197..51d8faf6fd1a 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -283,6 +283,7 @@ struct iris_platform_data {
u32 tz_cp_config_data_size;
u32 num_vpp_pipe;
bool no_aon;
+ u32 wd_intr_mask;
u32 max_session_count;
/* max number of macroblocks per frame supported */
u32 max_core_mbpf;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
index 8259709ba203..238c7b17ed4f 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
@@ -16,6 +16,8 @@
#include "iris_platform_sc7280.h"
#include "iris_platform_sm8250.h"
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
+
const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = {
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
@@ -94,6 +96,7 @@ const struct iris_platform_data sc7280_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 1,
.no_aon = true,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
/* max spec for SC7280 is 4096x2176@60fps */
@@ -124,6 +127,7 @@ const struct iris_platform_data sm8250_data = {
.tz_cp_config_data = tz_cp_config_vpu2,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
index 829dc37b4058..6e63f279efbe 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
@@ -17,6 +17,8 @@
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
+
const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = {
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
@@ -106,6 +108,7 @@ const struct iris_platform_data qcs8300_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 2,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = ((4096 * 2176) / 256) * 4,
.max_core_mbps = (((3840 * 2176) / 256) * 120),
@@ -135,6 +138,7 @@ const struct iris_platform_data sm8550_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -172,6 +176,7 @@ const struct iris_platform_data sm8650_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -201,6 +206,7 @@ const struct iris_platform_data sm8750_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 59e4d68d042f..b8300195a43b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core)
void iris_vpu_clear_interrupt(struct iris_core *core)
{
+ u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
u32 intr_status, mask;
intr_status = readl(core->reg_base + WRAPPER_INTR_STATUS);
- mask = (WRAPPER_INTR_STATUS_A2H_BMSK |
- WRAPPER_INTR_STATUS_A2HWD_BMSK |
+ mask = (WRAPPER_INTR_STATUS_A2H_BMSK | wd_intr_mask |
CTRL_INIT_IDLE_MSG_BMSK);
if (intr_status & mask)
@@ -124,7 +124,9 @@ void iris_vpu_clear_interrupt(struct iris_core *core)
int iris_vpu_watchdog(struct iris_core *core, u32 intr_status)
{
- if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK) {
+ u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
+
+ if (intr_status & wd_intr_mask) {
dev_err(core->dev, "received watchdog interrupt\n");
return -ETIME;
}
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index 72168b9ffa73..4fffa094c52f 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -41,7 +41,6 @@
#define MSK_CORE_POWER_ON BIT(1)
#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
-#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
--
2.47.3