[PATCH] drm/i915/gt: fix up region size calculation for flushing dcache lines

[Fedor Pchelkin]

Computing region size for flushing dcache lines currently involves

  execlists->csb_size * sizeof(execlists->csb_status)

while the second operand should represent the size of the csb status array
element (u64), not the size of the pointer variable.  It works on a 64-bit
kernel, but it's not correct for exotic 32-bit ones and may result in an
incomplete flush when the number of csb entries covers more than a single
cacheline.

Found by Linux Verification Center (linuxtesting.org) with Svace static
analysis tool.

Fixes: dc0406820ee7 ("drm/i915/gt: Drop invalidate_csb_entries")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Fedor Pchelkin <pchelkin@xxxxxxxxx>
---

The patch is against drm-intel/drm-intel-next,
HEAD:775fb670745015d679a65f948b3da0fbff3f100c

 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 1359fc9cb88e..31037ee3c2c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2833,7 +2833,7 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
 	memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
 	drm_clflush_virt_range(execlists->csb_status,
 			       execlists->csb_size *
-			       sizeof(execlists->csb_status));
+			       sizeof(execlists->csb_status[0]));
 
 	/* Once more for luck and our trusty paranoia */
 	ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
-- 
2.53.0