[PATCH v7 02/13] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC

[Tommaso Merciai]

The RZ/G3E SoC integrates two LCD controllers (LCDC0 and LCDC1), each
containing a FCPVD, VSPD, and Display Unit (DU).

 - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
 - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.

Add compatible string 'renesas,r9a09g047-du' and extend the binding to
support two DU instances: add reg-names ('du0'/'du1'), extend reg,
interrupts, and resets to maxItems: 2, and extend clocks/clock-names to
six entries (aclk/pclk/vclk per instance, minItems: 3).

Drop the "Each port shall have a single endpoint." constraint since
RZ/G3E ports expose multiple endpoints.

Add a RZ/G3E-specific allOf rule mapping two DU instances to two ports:

 - port@0 (DU0): endpoint@0 DSI, endpoint@2 LVDS ch0, endpoint@3 LVDS ch1
 - port@1 (DU1): endpoint@0 DSI, endpoint@1 RGB (DPAD), endpoint@3 LVDS ch1

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
---
v6->v7:
 - Rebased on top of [1]
   [1] https://lore.kernel.org/all/20260429170012.366537-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
 - Use single DRM device aggregating both DU instances (1 DU dt node),
   modelling single port for each DU0, DU1 and multiple endpoints for
   outputs.

v5->v6:
 - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
   explicitly disable port@2 and port@3 for existing SoCs that do not expose
   them.
 - Reworked ports numbering + improved/fixed ports descriptions in the
   bindings documentation.
 - Improved commit body.

v4->v5:
 - Dropped renesas,id property and updated bindings
   accordingly.

v2->v3:
 - No changes.

v2->v3:
 - No changes.

v1->v2:
 - Use single compatible string instead of multiple compatible strings
   for the two DU instances, leveraging a 'renesas,id' property to
   differentiate between DU0 and DU1.
 - Updated commit message accordingly.

 .../bindings/display/renesas,rzg2l-du.yaml    | 134 +++++++++++++++++-
 1 file changed, 130 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 0d7df210407b..8ad1361a0f3a 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -20,6 +20,7 @@ properties:
       - enum:
           - renesas,r9a07g043u-du # RZ/G2UL
           - renesas,r9a07g044-du # RZ/G2{L,LC}
+          - renesas,r9a09g047-du # RZ/G3E
           - renesas,r9a09g057-du # RZ/V2H(P)
           - renesas,r9a09g077-du # RZ/T2H
       - items:
@@ -34,25 +35,47 @@ properties:
           - const: renesas,r9a09g077-du # RZ/T2H fallback
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: du0
+      - const: du1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   clocks:
+    minItems: 3
     items:
       - description: Main clock
       - description: Register access clock
       - description: Video clock
+      - description: Main clock for DU1
+      - description: Register access clock for DU1
+      - description: Video clock for DU1
 
   clock-names:
+    minItems: 3
     items:
       - const: aclk
       - const: pclk
       - const: vclk
+      - const: aclk1
+      - const: pclk1
+      - const: vclk1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    minItems: 1
+    items:
+      - const: resetn
+      - const: resetn1
 
   power-domains:
     maxItems: 1
@@ -66,7 +89,7 @@ properties:
     description: |
       The connections to the DU output video ports are modeled using the OF
       graph bindings. The number of ports and their assignment are
-      model-dependent. Each port shall have a single endpoint.
+      model-dependent.
 
     patternProperties:
       "^port@[0-1]$":
@@ -104,6 +127,18 @@ allOf:
             const: renesas,r9a07g043u-du
     then:
       properties:
+        reg:
+          maxItems: 1
+        reg-names: false
+        interrupts:
+          maxItems: 1
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
+        resets:
+          maxItems: 1
+        reset-names: false
         ports:
           properties:
             port@0:
@@ -119,6 +154,18 @@ allOf:
             const: renesas,r9a07g044-du
     then:
       properties:
+        reg:
+          maxItems: 1
+        reg-names: false
+        interrupts:
+          maxItems: 1
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
+        resets:
+          maxItems: 1
+        reset-names: false
         ports:
           properties:
             port@0:
@@ -136,6 +183,18 @@ allOf:
             const: renesas,r9a09g057-du
     then:
       properties:
+        reg:
+          maxItems: 1
+        reg-names: false
+        interrupts:
+          maxItems: 1
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
+        resets:
+          maxItems: 1
+        reset-names: false
         ports:
           properties:
             port@0:
@@ -151,7 +210,17 @@ allOf:
             const: renesas,r9a09g077-du
     then:
       properties:
+        reg:
+          maxItems: 1
+        reg-names: false
+        interrupts:
+          maxItems: 1
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
         resets: false
+        reset-names: false
       required:
         - port
     else:
@@ -159,6 +228,63 @@ allOf:
         - resets
         - ports
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-du
+    then:
+      properties:
+        reg:
+          minItems: 2
+        interrupts:
+          minItems: 2
+        clocks:
+          minItems: 6
+        clock-names:
+          minItems: 6
+        reg-names:
+          minItems: 2
+        resets:
+          minItems: 2
+        reset-names:
+          minItems: 2
+        ports:
+          properties:
+            port@0:
+              description: DU0 outputs
+              properties:
+                endpoint@0:
+                  description: DSI
+                endpoint@2:
+                  description: LVDS, Channel 0
+                endpoint@3:
+                  description: LVDS, Channel 1
+              required:
+                - endpoint@0
+                - endpoint@2
+                - endpoint@3
+            port@1:
+              description: DU1 outputs
+              properties:
+                endpoint@0:
+                  description: DSI
+                endpoint@1:
+                  description: RGB (DPAD)
+                endpoint@3:
+                  description: LVDS, Channel 1
+              required:
+                - endpoint@0
+                - endpoint@1
+                - endpoint@3
+
+          required:
+            - port@0
+            - port@1
+      required:
+        - reg-names
+        - reset-names
+
 examples:
   # RZ/G2L DU
   - |
-- 
2.54.0