Re: [PATCH] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs

[Peter Griffin]

On Tue, 5 May 2026 at 18:15, Kuan-Wei Chiu <visitorckw@xxxxxxxxx> wrote:
>
> In the peric0_clk_regs array, the divider register offset for USI6 was
> accidentally listed twice, while the divider for USI7 was omitted.
>
> Missing this DIV register causes the USI7 clock divider setting to be
> lost and reset to its hardware default value during a suspend/resume
> cycle.
>
> Replace the duplicated USI6 DIV entry with the correct USI7 DIV
> register.
>
> Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0")
> Signed-off-by: Kuan-Wei Chiu <visitorckw@xxxxxxxxx>
> ---

Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>