RE: [PATCH 3/3] clk: renesas: r9a08g046: Add RSPI clock and reset support

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 07 May 2026 13:46
> Subject: Re: [PATCH 3/3] clk: renesas: r9a08g046: Add RSPI clock and reset support
> 
> Hi Biju,
> 
> On Tue, 5 May 2026 at 09:15, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add clock and reset definitions for the three RSPI (Serial Peripheral
> > Interface) channels on the RZ/G3L (R9A08G046) SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r9a08g046-cpg.c
> > +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> > @@ -168,6 +190,7 @@ static const char * const sel_eth1_tx[] = {
> > ".div_eth1_tr", "eth1_txc_tx_clk" };  static const char * const
> > sel_eth1_rx[] = { ".div_eth1_tr", "eth1_rxc_rx_clk" };  static const
> > char * const sel_eth1_rm[] = { ".pll6_div10", "eth1_rxc_rx_clk" };
> > static const char * const sel_rsci[] = { ".pll2_div5", ".pll2_div6",
> > ".pll2_div7", ".pll2_div2_4" };
> > +static const char * const sel_rspi[] = { ".pll2_div5", ".pll2_div6",
> > +".pll2_div7", ".pll2_div2_4" };
> 
> OK if I drop this line...

Agreed.

> 
> >  static const char * const sel_eth0_clk_tx_i[] = { ".sel_eth0_tx",
> > ".div_eth0_rm" };  static const char * const sel_eth0_clk_rx_i[] = {
> > ".sel_eth0_rx", ".div_eth0_rm" };  static const char * const
> > sel_eth1_clk_tx_i[] = { ".sel_eth1_tx", ".div_eth1_rm" }; @@ -199,6 +222,9 @@ static const struct
> cpg_core_clk r9a08g046_core_clks[] __initconst = {
> >         DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci),
> >         DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci),
> >         DEF_MUX(".sel_rsci3", CLK_SEL_RSCI3, G3L_SEL_RSCI3, sel_rsci),
> > +       DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rspi),
> > +       DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rspi),
> > +       DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rspi),
> 
> ... and s/sel_rspi/sel_rsci_rspi/ while applying?

OK. 

Thank you,
Biju

> 
> >         DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
> >         DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
> >         DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM,
> > sel_eth0_rm),
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> i.e. will queue in renesas-clk for v7.2.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds