[PATCH] KVM: selftests: Add guest-side test for AMD HWCR.McStatusWrEn

[Costas Argyris]

The existing hwcr_msr_test exercises MSR_K7_HWCR only via KVM_SET_MSRS,
which sets host_initiated=true in KVM. The gate in set_msr_mce() that
calls can_set_mci_status() short-circuits when host_initiated=true, so
can_set_mci_status() is never reached by the existing test.

Add a guest-side test that verifies HWCR.McStatusWrEn (bit 18) correctly
gates non-zero writes to MCi_STATUS MSRs. With the bit set, the write
must succeed and read back unchanged. With the bit clear, the write must
raise #GP and leave the register unmodified.

Signed-off-by: Costas Argyris <costas.argyris@xxxxxxx>
---
 .../testing/selftests/kvm/x86/hwcr_msr_test.c | 65 ++++++++++++++++++-
 1 file changed, 63 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
index 10b1b0ba374e..4e249bffcbb1 100644
--- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
+++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
@@ -6,9 +6,9 @@
 
 #include "test_util.h"
 #include "kvm_util.h"
-#include "vmx.h"
+#include "processor.h"
 
-void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit)
+static void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit)
 {
 	const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8);
 	const uint64_t valid = BIT_ULL(18) | BIT_ULL(24);
@@ -30,6 +30,61 @@ void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit)
 	vcpu_set_msr(vcpu, MSR_K7_HWCR, 0);
 }
 
+/*
+ * AMD-specific: test that HWCR.McStatusWrEn (bit 18) gates guest writes to
+ * MCi_STATUS MSRs.  With the bit set, a non-zero write to MC0_STATUS must
+ * succeed and read back unchanged.  With the bit clear, the write must take
+ * a #GP.
+ *
+ * This exercises arch/x86/kvm/x86.c:can_set_mci_status(), which is only
+ * reachable via the guest WRMSR path (host_initiated=false); test_hwcr_bit()
+ * uses KVM_SET_MSRS (host_initiated=true) and never triggers it.
+ */
+static void guest_code(void)
+{
+	uint8_t vector;
+	uint64_t val;
+
+	/* McStatusWrEn=1: non-zero write to MCi_STATUS must succeed. */
+	wrmsr(MSR_K7_HWCR, BIT_ULL(18));
+	wrmsr(MSR_IA32_MC0_STATUS, 1);
+	val = rdmsr(MSR_IA32_MC0_STATUS);
+	GUEST_ASSERT_EQ(val, 1);
+
+	/* Clear the status register before disabling the write-enable bit. */
+	wrmsr(MSR_IA32_MC0_STATUS, 0);
+
+	/* McStatusWrEn=0: non-zero write to MCi_STATUS must #GP. */
+	wrmsr(MSR_K7_HWCR, 0);
+	vector = wrmsr_safe(MSR_IA32_MC0_STATUS, 1);
+	GUEST_ASSERT_EQ(vector, GP_VECTOR);
+
+	/* Confirm the failed write left the register at zero. */
+	val = rdmsr(MSR_IA32_MC0_STATUS);
+	GUEST_ASSERT_EQ(val, 0);
+
+	GUEST_DONE();
+}
+
+static void enter_guest(struct kvm_vcpu *vcpu)
+{
+	struct ucall uc;
+
+	while (true) {
+		vcpu_run(vcpu);
+		TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
+
+		switch (get_ucall(vcpu, &uc)) {
+		case UCALL_DONE:
+			return;
+		case UCALL_ABORT:
+			REPORT_GUEST_ASSERT(uc);
+		default:
+			TEST_FAIL("Unexpected ucall %lu", uc.cmd);
+		}
+	}
+}
+
 int main(int argc, char *argv[])
 {
 	struct kvm_vm *vm;
@@ -42,4 +97,10 @@ int main(int argc, char *argv[])
 		test_hwcr_bit(vcpu, bit);
 
 	kvm_vm_free(vm);
+
+	if (host_cpu_is_amd_compatible) {
+		vm = vm_create_with_one_vcpu(&vcpu, guest_code);
+		enter_guest(vcpu);
+		kvm_vm_free(vm);
+	}
 }
-- 
2.43.0