Re: [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link

[Hans Zhang]

On 5/13/26 16:25, Aksh Garg wrote:
> > > Hi Hans,
> > >
> > > The LTSSM state encoding in your patches do not align with the state 
> > > encodings for LGA IP. TI SoCs have LGA IP of Cadence PCIe, and when I
> > > applied your patches, the LTSSM value in the debugfs for the PCIe
> > > subsystem (which have an EP connected to it) came out to be 0x10, which
> > > points to the state "PCIE_L0". However, the debugfs prints the state as
> > > "POLLING_CONFIG_2 (0x10)", which seems to be incorrect.
> > >
> > > The LTSSM state encodings for TI SoCs using Cadence PCIe IP is 
> > > provided in the J7200 TRM section 12.2.3.4.14 at:
> > > https://www.ti.com/lit/pdf/spruiu1
> >
> > Hi Aksh,
> >
> > Thank you for the information you provided. Could you please tell me 
> > how to read this register? Then I will incorporate it into the next 
> > version.
>
> The code to read the LTSSM state for LGA IPs in your patch:
> ```
> reg = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
> ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, reg);
> ```
> correctly reads the LTSSM state for TI SoCs which uses LGA IP.

Hi Aksh,


Thank you.


Best regards,
Hans