Re: [PATCH 2/4] clk: renesas: r8a73a4: Implement ZT/ZTR trace clock on R-Mobile APE6

[Marek Vasut]

On 5/13/26 3:15 PM, Geert Uytterhoeven wrote:

Hello Geert,

> On Sat, 2 May 2026 at 20:56, Marek Vasut
> <marek.vasut+renesas@xxxxxxxxxxx> wrote:
> > Implement ZT trace bus and ZTR trace clock on the R-Mobile APE6.
> >
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
>
> Thanks for your patch!
>
> /sys/kernel/debug/clk/clk_summary looks a bit off to me:
>
>      zt                         0       0        0        208000000
>      ztr                        0       0        0        277333334
>
> > --- a/drivers/clk/renesas/clk-r8a73a4.c
> > +++ b/drivers/clk/renesas/clk-r8a73a4.c
> > @@ -43,6 +43,8 @@ static struct div4_clk div4_clks[] = {
> >          { "m1", CPG_FRQCRA,  4 },
> >          { "m2", CPG_FRQCRA,  0 },
> >          { "zx", CPG_FRQCRB, 12 },
> > +       { "ztr", CPG_FRQCRB, 16 },
>
> 20?
>
> > +       { "zt", CPG_FRQCRB, 12 },
>
> 16? (12 is zx, cfr. above).
>
> I.e. the same shifts as on R-Mobile A1.
>
> >          { "zs", CPG_FRQCRB,  8 },
> >          { "hp", CPG_FRQCRB,  4 },
> >          { NULL, 0, 0 },
>
> After fixing the shifts, I get:
>
>      zt                         0       0        0        277333334
>      ztr                        0       0        0        277333334
>
> which looks much better. If you agree, I can fix this while applying.

Yes please. I can confirm in APE6 RM v0.7 that the ZTFC is at bit offset 
16 and ZTRFC at bit offset 20 . Thank you for spotting this.

--
Best regards,
Marek Vasut