Re: [PATCH v3 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur

[Qiang Yu]

On Mon, May 18, 2026 at 08:59:14AM +0200, Krzysztof Kozlowski wrote:
> On 18/05/2026 05:35, Qiang Yu wrote:
> > On Sun, May 17, 2026 at 10:28:48AM +0200, Krzysztof Kozlowski wrote:
> >> On 17/05/2026 07:58, Qiang Yu wrote:
> >>> On Thu, May 14, 2026 at 12:35:19PM +0200, Krzysztof Kozlowski wrote:
> >>>> On 14/05/2026 12:22, Krzysztof Kozlowski wrote:
> >>>>> On Wed, May 06, 2026 at 01:43:51AM -0700, Qiang Yu wrote:
> >>>>>> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks
> >>>>>> required by clkref clocks.
> >>>>>>
> >>>>>> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common
> >>>>>> QREF TX/RPT/RX components, while SoC-specific topology and instance count
> >>>>>> differ. Document them here for qcom,glymur-tcsr.
> >>>>>>
> >>>>>> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> >>>>>> ---
> >>>>>>  .../bindings/clock/qcom,sm8550-tcsr.yaml           | 57 ++++++++++++++++++++++
> >>>>>>  1 file changed, 57 insertions(+)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> >>>>>> index 1ccdf4b0f5dd..57921cb63230 100644
> >>>>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> >>>>>> @@ -51,6 +51,63 @@ properties:
> >>>>>>    '#reset-cells':
> >>>>>>      const: 1
> >>>>>>  
> >>>>>> +  vdda-refgen-0p9-supply: true
> >>>>>> +  vdda-refgen-1p2-supply: true
> >>>>>> +  vdda-qrefrx0-0p9-supply: true
> >>>>>> +  vdda-qrefrx1-0p9-supply: true
> >>>>>> +  vdda-qrefrx2-0p9-supply: true
> >>>>>> +  vdda-qrefrx4-0p9-supply: true
> >>>>>> +  vdda-qrefrx5-0p9-supply: true
> >>>>>> +  vdda-qreftx0-0p9-supply: true
> >>>>>> +  vdda-qreftx0-1p2-supply: true
> >>>>>> +  vdda-qreftx1-0p9-supply: true
> >>>>>> +  vdda-qrefrpt0-0p9-supply: true
> >>>>>> +  vdda-qrefrpt1-0p9-supply: true
> >>>>>> +  vdda-qrefrpt2-0p9-supply: true
> >>>>>> +  vdda-qrefrpt3-0p9-supply: true
> >>>>>> +  vdda-qrefrpt4-0p9-supply: true
> >>>>>
> >>>>> Either I do not understand your previous explanation:
> >>>>> CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY
> >>>>>
> >>>>> or this is still wrong. There is no TCSR here, so this proves nothing.
> >>>>> If TCSR is TX0, then you do not have five of them...
> >>>>>
> >>>>> My previous comment stay - you are not describing the actual hardware
> >>>>> here.
> >>>>
> >>>> And it should not be my task BUT YOURS to verify this in hardware
> >>>> programming guide or manual, but nevertheless I did verify and the
> >>>> manual DOES NOT mention these supplies. For Glymur, it mentions 8 reset
> >>>> ports and 5 clock ports.
> >>>>
> >>>> No supplies at all.
> >>>>
> >>>> Then I went to QREF and it does mention few supplies but completely
> >>>> different, like mx, cx, px 0.88 and px1.2, so none of this matches QREF
> >>>> either.
> >>>>
> >>>
> >>> Honestly, I couldn't find QREF LDO-related information in HPG either.
> >>> However, you can find it on IPCAT. For example, in the glymur power grid,
> >>> these LDOs are clearly documented under the LDOs required by each PHY,
> >>
> >> How is that relevant here? This is not PHY here. You are adding supplies
> >> to TCSR. Do you understand what a supply is?
> >>
> > 
> > I'm telling you the fact that I see from power grid table.
> 
> So you see supplies in phy, then add them to the phy.

These LDOs don't supply to PHY directly and this is why I was taught to
add them in TCSR.

- Qiang Yu

> 
> Best regards,
> Krzysztof