Re: [PATCH v5 4/4] phy: ti-pipe3: Fix clock leak in init error path

[Hongling Zeng]

--
Sashiko AI review ·https://sashiko.dev/#/patchset/20260518062938.48114-1-zenghongling@xxxxxxxxxx?part=4
--
Hi:
 Resend to fix threading / delivery issues.
  Thank you for identifying these SATA mode issues. Both are pre-existing bugs in
  the current codebase and were not introduced by this series.

  This series focuses on specific EPROBE_DEFER and resource leak fixes. The SATA
  mode issues you've found are valid but affect different code paths and should be
  addressed separately to keep the patch series focused.

  I can submit follow-up patches to fix these SATA mode issues. Would you prefer
  them in v6 or as separate patches after this series?

  Best regards,
  Hongling
 

在 2026年05月18日 14:29, Hongling Zeng 写道:
> When regmap_update_bits() fails in ti_pipe3_init() for PCIe mode,
> the function returns the error without calling ti_pipe3_disable_clocks().
> This leaves the clocks permanently enabled since the PHY framework won't
> invoke the .exit callback on init failure.
>
> Fix this by adding proper clock cleanup in the PCIe error path, consistent
> with how the DPLL program error path handles cleanup.
>
> Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
> Reported-by: Sashiko AI <sashiko@xxxxxxxxxx>
> Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@xxxxxxxxxxxxxxx/
> Signed-off-by: Hongling Zeng <zenghongling@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
>
> ---
> Change in v5:
>    -Add Fix ignored clock enable return value in init patch
> ---
>   drivers/phy/ti/phy-ti-pipe3.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
> index 9ec228c2a940..4897e4ba2d7d 100644
> --- a/drivers/phy/ti/phy-ti-pipe3.c
> +++ b/drivers/phy/ti/phy-ti-pipe3.c
> @@ -518,6 +518,8 @@ static int ti_pipe3_init(struct phy *x)
>   		val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
>   		ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
>   					 PCIE_PCS_MASK, val);
> +		if (ret)
> +			ti_pipe3_disable_clocks(phy);
>   		return ret;
>   	}
>