Re: [PATCH v1 3/3] arm64: dts: qcom: Add Vicharak Axon Mini

[Ajit Singh]

On Mon, May 18, 2026 at 01:44:25PM +0530, Konrad Dybcio wrote:
> On 5/18/26 1:04 PM, Ajit Singh wrote:
> > Add DTS for the Vicharak Axon Mini board based on the Qualcomm
> > QCS6490 SoC.
> > 
> > This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe,
> > support along with regulators.
> > 
> > Signed-off-by: Ajit Singh <blfizzyy@xxxxxxxxx>
> > ---
> 
> Hello, this looks good overall, I have a couple comments below
> 
> [...]
> 
> > +	vcc_3v3: regulator-vcc-3v3 {
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "vcc_3v3";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +
> > +		vin-supply = <&vcc_5v0>;
> > +
> > +		gpio = <&tlmm 113 GPIO_ACTIVE_HIGH>;
> > +		enable-active-high;
> > +
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&vcc_3v3_en>;
> 
> nit: Please put 
> 
> property-n
> property-names
> 
> in this order, consistently
> 
> [...]
> 
> > +&usb_2 {
> > +	dr_mode = "host";
> > +	status = "okay";
> 
> Let's also keep a \n before the 'status' property, file-wide
> 
> > +};
> > +
> > +&eud {
> > +	status = "disabled";
> > +};
> 
> It's already disabled in kodiak.dtsi, you can drop this override
> 
> > +
> > +&usb_2_hsphy {
> 
> Please sort the top-level &label references alphabetically
> 
> [...]
> 
> > +&ice {
> > +	status = "disabled";
> 
> It should be working fine, any reason?
ICE is kept disabled because enabling the ICE node currently causes a
fatal SError during ICE probe on this board:

    qcom_ice_create+0x90/0x274 [qcom_ice]
    qcom_ice_probe+0x38/0x80 [qcom_ice]
    Kernel panic - not syncing: Asynchronous SError Interrupt

UFS works without ICE, so I kept ICE disabled for the initial board
support.
> 
> [...]
> 
> > +&ufs_mem_hc {
> > +	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
> > +	vcc-supply = <&vreg_l7b_2p96>;
> > +	vcc-max-microamp = <800000>;
> > +	vccq-supply = <&vreg_l9b_1p2>;
> > +	vccq-max-microamp = <900000>;
> > +	vccq2-supply = <&vreg_l9b_1p2>;
> > +	vccq2-max-microamp = <900000>;
> > +
> > +	status = "okay";
> > +
> > +	/delete-property/ qcom,ice;
> 
> similarly here
> 
> [...]
> 
> > +&pcie0 {
> > +	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
> > +	wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
> > +
> > +	pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
> > +	pinctrl-names = "default";
> > +
> > +	status = "okay";
> 
> Is there anything interesting connected to these buses?
PCIe0 is routed to the onboard NVMe slot. PCIe1 is routed to the
modular HAT connector, where the attached endpoint depends on the HAT
module, for example Ethernet or USB.
> 
> Konrad