Re: [PATCH v9 09/23] coco/tdx-host: Don't expose P-SEAMLDR information on CPUs with erratum

[Dave Hansen]

On 5/18/26 05:44, Chao Gao wrote:
> On Fri, May 15, 2026 at 10:26:19AM -0700, Dave Hansen wrote:
>> On 5/13/26 08:09, Chao Gao wrote:
>>> Some TDX-capable CPUs have an erratum, as documented in Intel® Trust
>>> Domain CPU Architectural Extensions (May 2021 edition) Chapter 2.3:
>> 2021, eh?
> The TDX ISA document has not been updated since then; the May 2021
> edition is still the latest revision. See:
> 
> https://www.intel.com/content/www/us/en/developer/tools/trust-domain-
> extensions/documentation.html

I think you are saying that the CPUs have an erratum.

That erratum diverges their implementation from the spec: "Intel® Trust
Domain CPU Architectural Extensions (May 2021 edition) Chapter 2.3".

But when you combine those two things in one sentence, it's incredibly
confusing.

The erratum you are talking about is brand new. I just asked for it to
be created in the last month or two. Thus, my confusion when you say
there: "an erratum, as documented in ... May 2021".

Thus, I'm questioning the 2021 date. You probably also want to mention
that the erratum is, as of today, not publicly documented.

Can you rephrase this all and make it clearer, please?