Re: [PATCH v2 2/2] PCI: Wait for device readiness after D3hot -> D0uninitialized transition

[Rafael J. Wysocki]

On Mon, May 18, 2026 at 9:46 PM Lukas Wunner <lukas@xxxxxxxxx> wrote:
>
> On Mon, May 18, 2026 at 09:38:12PM +0200, Rafael J. Wysocki wrote:
> > On Mon, May 18, 2026 at 9:12 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> > > +++ b/drivers/pci/pci.c
> > > @@ -1341,10 +1352,19 @@ int pci_power_up(struct pci_dev *dev)
> > >         pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
> > >
> > >         /* Mandatory transition delays; see PCI PM 1.2. */
> > > -       if (state == PCI_D3hot)
> > > +       if (state == PCI_D3hot) {
> > >                 pci_dev_d3_sleep(dev);
> > > -       else if (state == PCI_D2)
> > > +               if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) {
> >
> > Hmm.  The pmcsr value here is from before the pci_write_config_word(),
> > so AFAICS it should be updated after the write.
>
> The No_Soft_Reset bit is RO (PCIe r7.0 sec 7.5.2.2), so its value should
> never change when writing zero to the Power Management Control/Status
> Register.

Oh right, I confused it with something else.