Re: [PATCH 10/10] clk: amlogic: Add A9 AO clock controller driver

[Jian Hu]

On 5/15/2026 12:27 AM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@xxxxxxxxxx> wrote:
>
> > From: Jian Hu <jian.hu@xxxxxxxxxxx>
> >
> > Add the Always-on clock controller driver for the Amlogic A9 SoC family.
> >
> > Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
> > ---
> >   drivers/clk/meson/Makefile   |   2 +-
> >   drivers/clk/meson/a9-aoclk.c | 494 +++++++++++++++++++++++++++++++++++++++++++
> >   2 files changed, 495 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> > index 2b5b67b14efc..91af609ce815 100644
> > --- a/drivers/clk/meson/Makefile
> > +++ b/drivers/clk/meson/Makefile
> > @@ -20,7 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> >   obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> >   obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
> >   obj-$(CONFIG_COMMON_CLK_A9_PLL) += a9-pll.o
> > -obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o
> > +obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o a9-aoclk.o
> >   obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
> >   obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
> >   obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> > diff --git a/drivers/clk/meson/a9-aoclk.c b/drivers/clk/meson/a9-aoclk.c
> > new file mode 100644
> > index 000000000000..3c42eaf585d2
> > --- /dev/null
> > +++ b/drivers/clk/meson/a9-aoclk.c
> > @@ -0,0 +1,494 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> > +/*
> > + * Copyright (C) 2026 Amlogic, Inc. All rights reserved
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/amlogic,a9-aoclkc.h>
> > +#include "clk-regmap.h"
> > +#include "clk-dualdiv.h"
> > +#include "meson-clkc-utils.h"
> > +
> > +#define AO_OSCIN_CTRL                        0x00
> > +#define AO_SYS_CLK0                  0x04
> > +#define AO_PWM_CLK_A_CTRL            0x1c
> > +#define AO_PWM_CLK_B_CTRL            0x20
> > +#define AO_PWM_CLK_C_CTRL            0x24
> > +#define AO_PWM_CLK_D_CTRL            0x28
> > +#define AO_PWM_CLK_E_CTRL            0x2c
> > +#define AO_PWM_CLK_F_CTRL            0x30
> > +#define AO_PWM_CLK_G_CTRL            0x34
> > +#define AO_CEC_CTRL0                 0x38
> > +#define AO_CEC_CTRL1                 0x3c
> > +#define AO_RTC_BY_OSCIN_CTRL0                0x50
> > +#define AO_RTC_BY_OSCIN_CTRL1                0x54
> > +
> > +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
> > +     MESON_COMP_SEL(a9_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
>                         a9_ao_ ?

Ok, I will replace it with the prefix a9_ao_


[...]


Best regards,

Jian