Re: [PATCH v3 2/3] clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro

[Geert Uytterhoeven]

On Tue, 19 May 2026 at 16:15, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Replace the per-SoC G3S_PLL146_CONF() and G3L_PLL1467_CONF() macros with
> a unified CPG_PLL_CONF(stby, setting) macro defined in rzg2l-cpg.h.
>
> Drop the now-redundant GET_REG_SAMPLL_{CLK1, SETTING}() macros, replacing
> the latter with CPG_PLL1_SETTING_OFFSET() using FIELD_GET() to extract the
> offset value. Update RZG3L_PLL_{STBY,MON}_OFFSET() macros to derive
> offsets directly from CPG_PLL_STBY_OFFSET().
>
> No functional changes.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v2->v3:
>  * Rebased to renesas-clk and fixed the merge conflict.
> v1->v2:
>  * Updated commit description.
>  * Fixed the macro RZG3L_PLL_STBY_OFFSET by using CPG_PLL_STBY_OFFSET.

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.2.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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