[PATCH 2/3] arm64: dts: qcom: monaco-monza-som: Enable USB0 DRD mode
From: Akash Kumar
Date: Wed May 20 2026 - 05:44:30 EST
Enable USB0 dual-role mode on monza SOM using the Cypress CYPD6129 UCSI
controller.
Switch the controller node to I2C12, configure the required pinctrl and
interrupt settings, and wire the USB2/USB3 endpoints for the USB-C
connector.
Signed-off-by: Akash Kumar <akash.kumar@xxxxxxxxxxxxxxxx>
---
.../arm64/boot/dts/qcom/monaco-monza-som.dtsi | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
index 9b5ed55939b8..8e3af6018dfc 100644
--- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
@@ -194,6 +194,52 @@ &iris {
status = "okay";
};
+&i2c12 {
+ pinctrl-0 = <&qup_i2c12_data_clk>, <&usb0_intr_state>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ typec@8 {
+ compatible = "cypress,cypd6129";
+ reg = <0x08>;
+ interrupt-parent = <&tlmm>;
+ interrupts = < 3 IRQ_TYPE_LEVEL_LOW>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ccg_typec_con0: connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ucsi_ccg_hs: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ucsi_ccg_ss: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+ };
+};
+
/* PCIe0 Gen4 x2 */
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
@@ -227,6 +273,11 @@ &pcie1_phy {
status = "okay";
};
+&qup_i2c12_data_clk {
+ drive-strength = <2>;
+ bias-pull-up;
+};
+
&qupv3_id_0 {
firmware-name = "qcom/qcs8300/qupv3fw.elf";
@@ -295,6 +346,12 @@ dp_hpd: dp-hpd-state {
function = "edp0_hot";
bias-disable;
};
+
+ usb0_intr_state: usb0-intr-state {
+ pins = "gpio3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
/* USB0 HS + SS */
--
2.43.0