[PATCH 1/3] arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
From: Biju
Date: Wed May 20 2026 - 07:54:47 EST
From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043)
device tree.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index ded4f1f11d60..ce2023c01baa 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -656,6 +656,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@@ -672,6 +673,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
--
2.43.0