RE: [PATCH 1/2] arm64: dts: renesas: r9a08g046: Add RSPI{0..2} nodes

[Biju Das]

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 19 May 2026 12:20
> Subject: [PATCH 1/2] arm64: dts: renesas: r9a08g046: Add RSPI{0..2} nodes
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Add device tree nodes for the three RSPI channels on the RZ/G3L
> (R9A08G046) SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 72 ++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index a53d579eaad2..1fc409ebdd44 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -442,6 +442,78 @@ rsci3: serial@100f3000 {
>  			status = "disabled";
>  		};
> 
> +		rspi0: spi@100b0000 {
> +			compatible = "renesas,r9a08g046-rspi";
> +			reg = <0 0x100b0000 0 0x400>;

The size is 4K, so it should be 0x1000, same for othe nodes.

Cheers,
Biju

> +			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "idle", "error", "end", "rx", "tx";
> +			clocks = <&cpg CPG_MOD R9A08G046_RSPI0_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_RSPI0_TCLK>;
> +			clock-names = "pclk", "tclk";
> +			resets = <&cpg R9A08G046_RSPI0_PRESETN>,
> +				 <&cpg R9A08G046_RSPI0_TRESETN>;
> +			reset-names = "presetn", "tresetn";
> +			dmas = <&dmac 0x26f2>, <&dmac 0x26f1>;
> +			dma-names = "rx", "tx";
> +			power-domains = <&cpg>;
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		rspi1: spi@100e9000 {
> +			compatible = "renesas,r9a08g046-rspi";
> +			reg = <0 0x100e9000 0 0x400>;
> +			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "idle", "error", "end", "rx", "tx";
> +			clocks = <&cpg CPG_MOD R9A08G046_RSPI1_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_RSPI1_TCLK>;
> +			clock-names = "pclk", "tclk";
> +			resets = <&cpg R9A08G046_RSPI1_PRESETN>,
> +				 <&cpg R9A08G046_RSPI1_TRESETN>;
> +			reset-names = "presetn", "tresetn";
> +			dmas = <&dmac 0x26f6>, <&dmac 0x26f5>;
> +			dma-names = "rx", "tx";
> +			power-domains = <&cpg>;
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		rspi2: spi@100ea000 {
> +			compatible = "renesas,r9a08g046-rspi";
> +			reg = <0 0x100ea000 0 0x400>;
> +			interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 454 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "idle", "error", "end", "rx", "tx";
> +			clocks = <&cpg CPG_MOD R9A08G046_RSPI2_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_RSPI2_TCLK>;
> +			clock-names = "pclk", "tclk";
> +			resets = <&cpg R9A08G046_RSPI2_PRESETN>,
> +				 <&cpg R9A08G046_RSPI2_TRESETN>;
> +			reset-names = "presetn", "tresetn";
> +			dmas = <&dmac 0x26fa>, <&dmac 0x26f9>;
> +			dma-names = "rx", "tx";
> +			power-domains = <&cpg>;
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		canfd: can@100c0000 {
>  			reg = <0 0x100c0000 0 0x20000>;
>  			/* placeholder */
> --
> 2.43.0